/*******************************************************************************
* File Name: cydevice_trm.h
* 
* PSoC Creator  4.2
*
* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright (c) 2007-2018 Cypress Semiconductor.  All rights reserved.
* You may use this file only in accordance with the license, terms, conditions, 
* disclaimers, and limitations in the end user license agreement accompanying 
* the software package with which this file was provided.
********************************************************************************/

#if !defined(CYDEVICE_TRM_H)
#define CYDEVICE_TRM_H
#define CYDEV_FLASH_BASE 0x00000000u
#define CYDEV_FLASH_SIZE 0x00020000u
#define CYREG_FLASH_DATA_MBASE 0x00000000u
#define CYREG_FLASH_DATA_MSIZE 0x00020000u
#define CYDEV_SFLASH_BASE 0x0ffff000u
#define CYDEV_SFLASH_SIZE 0x00000800u
#define CYREG_SFLASH_PROT_ROW0 0x0ffff000u
#define CYFLD_SFLASH_DATA8__OFFSET 0x00000000u
#define CYFLD_SFLASH_DATA8__SIZE 0x00000008u
#define CYREG_SFLASH_PROT_ROW1 0x0ffff001u
#define CYREG_SFLASH_PROT_ROW2 0x0ffff002u
#define CYREG_SFLASH_PROT_ROW3 0x0ffff003u
#define CYREG_SFLASH_PROT_ROW4 0x0ffff004u
#define CYREG_SFLASH_PROT_ROW5 0x0ffff005u
#define CYREG_SFLASH_PROT_ROW6 0x0ffff006u
#define CYREG_SFLASH_PROT_ROW7 0x0ffff007u
#define CYREG_SFLASH_PROT_ROW8 0x0ffff008u
#define CYREG_SFLASH_PROT_ROW9 0x0ffff009u
#define CYREG_SFLASH_PROT_ROW10 0x0ffff00au
#define CYREG_SFLASH_PROT_ROW11 0x0ffff00bu
#define CYREG_SFLASH_PROT_ROW12 0x0ffff00cu
#define CYREG_SFLASH_PROT_ROW13 0x0ffff00du
#define CYREG_SFLASH_PROT_ROW14 0x0ffff00eu
#define CYREG_SFLASH_PROT_ROW15 0x0ffff00fu
#define CYREG_SFLASH_PROT_ROW16 0x0ffff010u
#define CYREG_SFLASH_PROT_ROW17 0x0ffff011u
#define CYREG_SFLASH_PROT_ROW18 0x0ffff012u
#define CYREG_SFLASH_PROT_ROW19 0x0ffff013u
#define CYREG_SFLASH_PROT_ROW20 0x0ffff014u
#define CYREG_SFLASH_PROT_ROW21 0x0ffff015u
#define CYREG_SFLASH_PROT_ROW22 0x0ffff016u
#define CYREG_SFLASH_PROT_ROW23 0x0ffff017u
#define CYREG_SFLASH_PROT_ROW24 0x0ffff018u
#define CYREG_SFLASH_PROT_ROW25 0x0ffff019u
#define CYREG_SFLASH_PROT_ROW26 0x0ffff01au
#define CYREG_SFLASH_PROT_ROW27 0x0ffff01bu
#define CYREG_SFLASH_PROT_ROW28 0x0ffff01cu
#define CYREG_SFLASH_PROT_ROW29 0x0ffff01du
#define CYREG_SFLASH_PROT_ROW30 0x0ffff01eu
#define CYREG_SFLASH_PROT_ROW31 0x0ffff01fu
#define CYREG_SFLASH_PROT_ROW32 0x0ffff020u
#define CYREG_SFLASH_PROT_ROW33 0x0ffff021u
#define CYREG_SFLASH_PROT_ROW34 0x0ffff022u
#define CYREG_SFLASH_PROT_ROW35 0x0ffff023u
#define CYREG_SFLASH_PROT_ROW36 0x0ffff024u
#define CYREG_SFLASH_PROT_ROW37 0x0ffff025u
#define CYREG_SFLASH_PROT_ROW38 0x0ffff026u
#define CYREG_SFLASH_PROT_ROW39 0x0ffff027u
#define CYREG_SFLASH_PROT_ROW40 0x0ffff028u
#define CYREG_SFLASH_PROT_ROW41 0x0ffff029u
#define CYREG_SFLASH_PROT_ROW42 0x0ffff02au
#define CYREG_SFLASH_PROT_ROW43 0x0ffff02bu
#define CYREG_SFLASH_PROT_ROW44 0x0ffff02cu
#define CYREG_SFLASH_PROT_ROW45 0x0ffff02du
#define CYREG_SFLASH_PROT_ROW46 0x0ffff02eu
#define CYREG_SFLASH_PROT_ROW47 0x0ffff02fu
#define CYREG_SFLASH_PROT_ROW48 0x0ffff030u
#define CYREG_SFLASH_PROT_ROW49 0x0ffff031u
#define CYREG_SFLASH_PROT_ROW50 0x0ffff032u
#define CYREG_SFLASH_PROT_ROW51 0x0ffff033u
#define CYREG_SFLASH_PROT_ROW52 0x0ffff034u
#define CYREG_SFLASH_PROT_ROW53 0x0ffff035u
#define CYREG_SFLASH_PROT_ROW54 0x0ffff036u
#define CYREG_SFLASH_PROT_ROW55 0x0ffff037u
#define CYREG_SFLASH_PROT_ROW56 0x0ffff038u
#define CYREG_SFLASH_PROT_ROW57 0x0ffff039u
#define CYREG_SFLASH_PROT_ROW58 0x0ffff03au
#define CYREG_SFLASH_PROT_ROW59 0x0ffff03bu
#define CYREG_SFLASH_PROT_ROW60 0x0ffff03cu
#define CYREG_SFLASH_PROT_ROW61 0x0ffff03du
#define CYREG_SFLASH_PROT_ROW62 0x0ffff03eu
#define CYREG_SFLASH_PROT_ROW63 0x0ffff03fu
#define CYREG_SFLASH_PROT_PROTECTION 0x0ffff0ffu
#define CYFLD_SFLASH_PROT_LEVEL__OFFSET 0x00000000u
#define CYFLD_SFLASH_PROT_LEVEL__SIZE 0x00000002u
#define CYVAL_SFLASH_PROT_LEVEL_VIRGIN 0x00000001u
#define CYVAL_SFLASH_PROT_LEVEL_OPEN 0x00000000u
#define CYVAL_SFLASH_PROT_LEVEL_PROTECTED 0x00000002u
#define CYVAL_SFLASH_PROT_LEVEL_KILL 0x00000003u
#define CYREG_SFLASH_AV_PAIRS_8B0 0x0ffff100u
#define CYREG_SFLASH_AV_PAIRS_8B1 0x0ffff101u
#define CYREG_SFLASH_AV_PAIRS_8B2 0x0ffff102u
#define CYREG_SFLASH_AV_PAIRS_8B3 0x0ffff103u
#define CYREG_SFLASH_AV_PAIRS_8B4 0x0ffff104u
#define CYREG_SFLASH_AV_PAIRS_8B5 0x0ffff105u
#define CYREG_SFLASH_AV_PAIRS_8B6 0x0ffff106u
#define CYREG_SFLASH_AV_PAIRS_8B7 0x0ffff107u
#define CYREG_SFLASH_AV_PAIRS_8B8 0x0ffff108u
#define CYREG_SFLASH_AV_PAIRS_8B9 0x0ffff109u
#define CYREG_SFLASH_AV_PAIRS_8B10 0x0ffff10au
#define CYREG_SFLASH_AV_PAIRS_8B11 0x0ffff10bu
#define CYREG_SFLASH_AV_PAIRS_8B12 0x0ffff10cu
#define CYREG_SFLASH_AV_PAIRS_8B13 0x0ffff10du
#define CYREG_SFLASH_AV_PAIRS_8B14 0x0ffff10eu
#define CYREG_SFLASH_AV_PAIRS_8B15 0x0ffff10fu
#define CYREG_SFLASH_AV_PAIRS_8B16 0x0ffff110u
#define CYREG_SFLASH_AV_PAIRS_8B17 0x0ffff111u
#define CYREG_SFLASH_AV_PAIRS_8B18 0x0ffff112u
#define CYREG_SFLASH_AV_PAIRS_8B19 0x0ffff113u
#define CYREG_SFLASH_AV_PAIRS_8B20 0x0ffff114u
#define CYREG_SFLASH_AV_PAIRS_8B21 0x0ffff115u
#define CYREG_SFLASH_AV_PAIRS_8B22 0x0ffff116u
#define CYREG_SFLASH_AV_PAIRS_8B23 0x0ffff117u
#define CYREG_SFLASH_AV_PAIRS_8B24 0x0ffff118u
#define CYREG_SFLASH_AV_PAIRS_8B25 0x0ffff119u
#define CYREG_SFLASH_AV_PAIRS_8B26 0x0ffff11au
#define CYREG_SFLASH_AV_PAIRS_8B27 0x0ffff11bu
#define CYREG_SFLASH_AV_PAIRS_8B28 0x0ffff11cu
#define CYREG_SFLASH_AV_PAIRS_8B29 0x0ffff11du
#define CYREG_SFLASH_AV_PAIRS_8B30 0x0ffff11eu
#define CYREG_SFLASH_AV_PAIRS_8B31 0x0ffff11fu
#define CYREG_SFLASH_AV_PAIRS_8B32 0x0ffff120u
#define CYREG_SFLASH_AV_PAIRS_8B33 0x0ffff121u
#define CYREG_SFLASH_AV_PAIRS_8B34 0x0ffff122u
#define CYREG_SFLASH_AV_PAIRS_8B35 0x0ffff123u
#define CYREG_SFLASH_AV_PAIRS_8B36 0x0ffff124u
#define CYREG_SFLASH_AV_PAIRS_8B37 0x0ffff125u
#define CYREG_SFLASH_AV_PAIRS_8B38 0x0ffff126u
#define CYREG_SFLASH_AV_PAIRS_8B39 0x0ffff127u
#define CYREG_SFLASH_AV_PAIRS_8B40 0x0ffff128u
#define CYREG_SFLASH_AV_PAIRS_8B41 0x0ffff129u
#define CYREG_SFLASH_AV_PAIRS_8B42 0x0ffff12au
#define CYREG_SFLASH_AV_PAIRS_8B43 0x0ffff12bu
#define CYREG_SFLASH_AV_PAIRS_8B44 0x0ffff12cu
#define CYREG_SFLASH_AV_PAIRS_8B45 0x0ffff12du
#define CYREG_SFLASH_AV_PAIRS_8B46 0x0ffff12eu
#define CYREG_SFLASH_AV_PAIRS_8B47 0x0ffff12fu
#define CYREG_SFLASH_AV_PAIRS_8B48 0x0ffff130u
#define CYREG_SFLASH_AV_PAIRS_8B49 0x0ffff131u
#define CYREG_SFLASH_AV_PAIRS_8B50 0x0ffff132u
#define CYREG_SFLASH_AV_PAIRS_8B51 0x0ffff133u
#define CYREG_SFLASH_AV_PAIRS_8B52 0x0ffff134u
#define CYREG_SFLASH_AV_PAIRS_8B53 0x0ffff135u
#define CYREG_SFLASH_AV_PAIRS_8B54 0x0ffff136u
#define CYREG_SFLASH_AV_PAIRS_8B55 0x0ffff137u
#define CYREG_SFLASH_AV_PAIRS_8B56 0x0ffff138u
#define CYREG_SFLASH_AV_PAIRS_8B57 0x0ffff139u
#define CYREG_SFLASH_AV_PAIRS_8B58 0x0ffff13au
#define CYREG_SFLASH_AV_PAIRS_8B59 0x0ffff13bu
#define CYREG_SFLASH_AV_PAIRS_8B60 0x0ffff13cu
#define CYREG_SFLASH_AV_PAIRS_8B61 0x0ffff13du
#define CYREG_SFLASH_AV_PAIRS_8B62 0x0ffff13eu
#define CYREG_SFLASH_AV_PAIRS_8B63 0x0ffff13fu
#define CYREG_SFLASH_AV_PAIRS_8B64 0x0ffff140u
#define CYREG_SFLASH_AV_PAIRS_8B65 0x0ffff141u
#define CYREG_SFLASH_AV_PAIRS_8B66 0x0ffff142u
#define CYREG_SFLASH_AV_PAIRS_8B67 0x0ffff143u
#define CYREG_SFLASH_AV_PAIRS_8B68 0x0ffff144u
#define CYREG_SFLASH_AV_PAIRS_8B69 0x0ffff145u
#define CYREG_SFLASH_AV_PAIRS_8B70 0x0ffff146u
#define CYREG_SFLASH_AV_PAIRS_8B71 0x0ffff147u
#define CYREG_SFLASH_AV_PAIRS_8B72 0x0ffff148u
#define CYREG_SFLASH_AV_PAIRS_8B73 0x0ffff149u
#define CYREG_SFLASH_AV_PAIRS_8B74 0x0ffff14au
#define CYREG_SFLASH_AV_PAIRS_8B75 0x0ffff14bu
#define CYREG_SFLASH_AV_PAIRS_8B76 0x0ffff14cu
#define CYREG_SFLASH_AV_PAIRS_8B77 0x0ffff14du
#define CYREG_SFLASH_AV_PAIRS_8B78 0x0ffff14eu
#define CYREG_SFLASH_AV_PAIRS_8B79 0x0ffff14fu
#define CYREG_SFLASH_AV_PAIRS_8B80 0x0ffff150u
#define CYREG_SFLASH_AV_PAIRS_8B81 0x0ffff151u
#define CYREG_SFLASH_AV_PAIRS_8B82 0x0ffff152u
#define CYREG_SFLASH_AV_PAIRS_8B83 0x0ffff153u
#define CYREG_SFLASH_AV_PAIRS_8B84 0x0ffff154u
#define CYREG_SFLASH_AV_PAIRS_8B85 0x0ffff155u
#define CYREG_SFLASH_AV_PAIRS_8B86 0x0ffff156u
#define CYREG_SFLASH_AV_PAIRS_8B87 0x0ffff157u
#define CYREG_SFLASH_AV_PAIRS_8B88 0x0ffff158u
#define CYREG_SFLASH_AV_PAIRS_8B89 0x0ffff159u
#define CYREG_SFLASH_AV_PAIRS_8B90 0x0ffff15au
#define CYREG_SFLASH_AV_PAIRS_8B91 0x0ffff15bu
#define CYREG_SFLASH_AV_PAIRS_8B92 0x0ffff15cu
#define CYREG_SFLASH_AV_PAIRS_8B93 0x0ffff15du
#define CYREG_SFLASH_AV_PAIRS_8B94 0x0ffff15eu
#define CYREG_SFLASH_AV_PAIRS_8B95 0x0ffff15fu
#define CYREG_SFLASH_AV_PAIRS_8B96 0x0ffff160u
#define CYREG_SFLASH_AV_PAIRS_8B97 0x0ffff161u
#define CYREG_SFLASH_AV_PAIRS_8B98 0x0ffff162u
#define CYREG_SFLASH_AV_PAIRS_8B99 0x0ffff163u
#define CYREG_SFLASH_AV_PAIRS_8B100 0x0ffff164u
#define CYREG_SFLASH_AV_PAIRS_8B101 0x0ffff165u
#define CYREG_SFLASH_AV_PAIRS_8B102 0x0ffff166u
#define CYREG_SFLASH_AV_PAIRS_8B103 0x0ffff167u
#define CYREG_SFLASH_AV_PAIRS_8B104 0x0ffff168u
#define CYREG_SFLASH_AV_PAIRS_8B105 0x0ffff169u
#define CYREG_SFLASH_AV_PAIRS_8B106 0x0ffff16au
#define CYREG_SFLASH_AV_PAIRS_8B107 0x0ffff16bu
#define CYREG_SFLASH_AV_PAIRS_8B108 0x0ffff16cu
#define CYREG_SFLASH_AV_PAIRS_8B109 0x0ffff16du
#define CYREG_SFLASH_AV_PAIRS_8B110 0x0ffff16eu
#define CYREG_SFLASH_AV_PAIRS_8B111 0x0ffff16fu
#define CYREG_SFLASH_AV_PAIRS_8B112 0x0ffff170u
#define CYREG_SFLASH_AV_PAIRS_8B113 0x0ffff171u
#define CYREG_SFLASH_AV_PAIRS_8B114 0x0ffff172u
#define CYREG_SFLASH_AV_PAIRS_8B115 0x0ffff173u
#define CYREG_SFLASH_AV_PAIRS_8B116 0x0ffff174u
#define CYREG_SFLASH_AV_PAIRS_8B117 0x0ffff175u
#define CYREG_SFLASH_AV_PAIRS_8B118 0x0ffff176u
#define CYREG_SFLASH_AV_PAIRS_8B119 0x0ffff177u
#define CYREG_SFLASH_AV_PAIRS_8B120 0x0ffff178u
#define CYREG_SFLASH_AV_PAIRS_8B121 0x0ffff179u
#define CYREG_SFLASH_AV_PAIRS_8B122 0x0ffff17au
#define CYREG_SFLASH_AV_PAIRS_8B123 0x0ffff17bu
#define CYREG_SFLASH_AV_PAIRS_8B124 0x0ffff17cu
#define CYREG_SFLASH_AV_PAIRS_8B125 0x0ffff17du
#define CYREG_SFLASH_AV_PAIRS_8B126 0x0ffff17eu
#define CYREG_SFLASH_AV_PAIRS_8B127 0x0ffff17fu
#define CYREG_SFLASH_AV_PAIRS_32B0 0x0ffff200u
#define CYFLD_SFLASH_DATA32__OFFSET 0x00000000u
#define CYFLD_SFLASH_DATA32__SIZE 0x00000020u
#define CYREG_SFLASH_AV_PAIRS_32B1 0x0ffff204u
#define CYREG_SFLASH_AV_PAIRS_32B2 0x0ffff208u
#define CYREG_SFLASH_AV_PAIRS_32B3 0x0ffff20cu
#define CYREG_SFLASH_AV_PAIRS_32B4 0x0ffff210u
#define CYREG_SFLASH_AV_PAIRS_32B5 0x0ffff214u
#define CYREG_SFLASH_AV_PAIRS_32B6 0x0ffff218u
#define CYREG_SFLASH_AV_PAIRS_32B7 0x0ffff21cu
#define CYREG_SFLASH_AV_PAIRS_32B8 0x0ffff220u
#define CYREG_SFLASH_AV_PAIRS_32B9 0x0ffff224u
#define CYREG_SFLASH_AV_PAIRS_32B10 0x0ffff228u
#define CYREG_SFLASH_AV_PAIRS_32B11 0x0ffff22cu
#define CYREG_SFLASH_AV_PAIRS_32B12 0x0ffff230u
#define CYREG_SFLASH_AV_PAIRS_32B13 0x0ffff234u
#define CYREG_SFLASH_AV_PAIRS_32B14 0x0ffff238u
#define CYREG_SFLASH_AV_PAIRS_32B15 0x0ffff23cu
#define CYREG_SFLASH_SILICON_ID 0x0ffff244u
#define CYFLD_SFLASH_ID__OFFSET 0x00000000u
#define CYFLD_SFLASH_ID__SIZE 0x00000010u
#define CYREG_SFLASH_HIB_KEY_DELAY 0x0ffff250u
#define CYFLD_SFLASH_WAKEUP_HOLDOFF__OFFSET 0x00000000u
#define CYFLD_SFLASH_WAKEUP_HOLDOFF__SIZE 0x0000000au
#define CYREG_SFLASH_DPSLP_KEY_DELAY 0x0ffff252u
#define CYREG_SFLASH_SWD_CONFIG 0x0ffff254u
#define CYFLD_SFLASH_SWD_SELECT__OFFSET 0x00000000u
#define CYFLD_SFLASH_SWD_SELECT__SIZE 0x00000001u
#define CYREG_SFLASH_SWD_LISTEN 0x0ffff258u
#define CYFLD_SFLASH_CYCLES__OFFSET 0x00000000u
#define CYFLD_SFLASH_CYCLES__SIZE 0x00000020u
#define CYREG_SFLASH_FLASH_START 0x0ffff25cu
#define CYFLD_SFLASH_ADDRESS__OFFSET 0x00000000u
#define CYFLD_SFLASH_ADDRESS__SIZE 0x00000020u
#define CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM1 0x0ffff260u
#define CYFLD_SFLASH_CSD_ADC_CAL_LSB__OFFSET 0x00000000u
#define CYFLD_SFLASH_CSD_ADC_CAL_LSB__SIZE 0x00000008u
#define CYREG_SFLASH_CSDV2_CSD0_ADC_TRIM2 0x0ffff261u
#define CYFLD_SFLASH_CSD_ADC_CAL_MSB__OFFSET 0x00000000u
#define CYFLD_SFLASH_CSD_ADC_CAL_MSB__SIZE 0x00000008u
#define CYREG_SFLASH_SAR_TEMP_MULTIPLIER 0x0ffff264u
#define CYFLD_SFLASH_TEMP_MULTIPLIER__OFFSET 0x00000000u
#define CYFLD_SFLASH_TEMP_MULTIPLIER__SIZE 0x00000010u
#define CYREG_SFLASH_SAR_TEMP_OFFSET 0x0ffff266u
#define CYFLD_SFLASH_TEMP_OFFSET__OFFSET 0x00000000u
#define CYFLD_SFLASH_TEMP_OFFSET__SIZE 0x00000010u
#define CYREG_SFLASH_PROT_VIRGINKEY0 0x0ffff270u
#define CYFLD_SFLASH_KEY8__OFFSET 0x00000000u
#define CYFLD_SFLASH_KEY8__SIZE 0x00000008u
#define CYREG_SFLASH_PROT_VIRGINKEY1 0x0ffff271u
#define CYREG_SFLASH_PROT_VIRGINKEY2 0x0ffff272u
#define CYREG_SFLASH_PROT_VIRGINKEY3 0x0ffff273u
#define CYREG_SFLASH_PROT_VIRGINKEY4 0x0ffff274u
#define CYREG_SFLASH_PROT_VIRGINKEY5 0x0ffff275u
#define CYREG_SFLASH_PROT_VIRGINKEY6 0x0ffff276u
#define CYREG_SFLASH_PROT_VIRGINKEY7 0x0ffff277u
#define CYREG_SFLASH_DIE_LOT0 0x0ffff278u
#define CYFLD_SFLASH_LOT__OFFSET 0x00000000u
#define CYFLD_SFLASH_LOT__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_LOT1 0x0ffff279u
#define CYREG_SFLASH_DIE_LOT2 0x0ffff27au
#define CYREG_SFLASH_DIE_WAFER 0x0ffff27bu
#define CYFLD_SFLASH_WAFER__OFFSET 0x00000000u
#define CYFLD_SFLASH_WAFER__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_X 0x0ffff27cu
#define CYFLD_SFLASH_X__OFFSET 0x00000000u
#define CYFLD_SFLASH_X__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_Y 0x0ffff27du
#define CYFLD_SFLASH_Y__OFFSET 0x00000000u
#define CYFLD_SFLASH_Y__SIZE 0x00000008u
#define CYREG_SFLASH_DIE_SORT 0x0ffff27eu
#define CYFLD_SFLASH_S1_PASS__OFFSET 0x00000000u
#define CYFLD_SFLASH_S1_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_S2_PASS__OFFSET 0x00000001u
#define CYFLD_SFLASH_S2_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_S3_PASS__OFFSET 0x00000002u
#define CYFLD_SFLASH_S3_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_CRI_PASS__OFFSET 0x00000003u
#define CYFLD_SFLASH_CRI_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_CHI_PASS__OFFSET 0x00000004u
#define CYFLD_SFLASH_CHI_PASS__SIZE 0x00000001u
#define CYFLD_SFLASH_ENG_PASS__OFFSET 0x00000005u
#define CYFLD_SFLASH_ENG_PASS__SIZE 0x00000001u
#define CYREG_SFLASH_DIE_MINOR 0x0ffff27fu
#define CYFLD_SFLASH_MINOR__OFFSET 0x00000000u
#define CYFLD_SFLASH_MINOR__SIZE 0x00000008u
#define CYREG_SFLASH_IMO_TRIM_USBMODE_24 0x0ffff33eu
#define CYFLD_SFLASH_TRIM_24__OFFSET 0x00000000u
#define CYFLD_SFLASH_TRIM_24__SIZE 0x00000008u
#define CYREG_SFLASH_IMO_TRIM_USBMODE_48 0x0ffff33fu
#define CYREG_SFLASH_IMO_TCTRIM_LT0 0x0ffff34cu
#define CYFLD_SFLASH_STEPSIZE__OFFSET 0x00000000u
#define CYFLD_SFLASH_STEPSIZE__SIZE 0x00000005u
#define CYFLD_SFLASH_TCTRIM__OFFSET 0x00000005u
#define CYFLD_SFLASH_TCTRIM__SIZE 0x00000002u
#define CYREG_SFLASH_IMO_TCTRIM_LT1 0x0ffff34du
#define CYREG_SFLASH_IMO_TCTRIM_LT2 0x0ffff34eu
#define CYREG_SFLASH_IMO_TCTRIM_LT3 0x0ffff34fu
#define CYREG_SFLASH_IMO_TCTRIM_LT4 0x0ffff350u
#define CYREG_SFLASH_IMO_TCTRIM_LT5 0x0ffff351u
#define CYREG_SFLASH_IMO_TCTRIM_LT6 0x0ffff352u
#define CYREG_SFLASH_IMO_TCTRIM_LT7 0x0ffff353u
#define CYREG_SFLASH_IMO_TCTRIM_LT8 0x0ffff354u
#define CYREG_SFLASH_IMO_TCTRIM_LT9 0x0ffff355u
#define CYREG_SFLASH_IMO_TCTRIM_LT10 0x0ffff356u
#define CYREG_SFLASH_IMO_TCTRIM_LT11 0x0ffff357u
#define CYREG_SFLASH_IMO_TCTRIM_LT12 0x0ffff358u
#define CYREG_SFLASH_IMO_TCTRIM_LT13 0x0ffff359u
#define CYREG_SFLASH_IMO_TCTRIM_LT14 0x0ffff35au
#define CYREG_SFLASH_IMO_TCTRIM_LT15 0x0ffff35bu
#define CYREG_SFLASH_IMO_TCTRIM_LT16 0x0ffff35cu
#define CYREG_SFLASH_IMO_TCTRIM_LT17 0x0ffff35du
#define CYREG_SFLASH_IMO_TCTRIM_LT18 0x0ffff35eu
#define CYREG_SFLASH_IMO_TCTRIM_LT19 0x0ffff35fu
#define CYREG_SFLASH_IMO_TCTRIM_LT20 0x0ffff360u
#define CYREG_SFLASH_IMO_TCTRIM_LT21 0x0ffff361u
#define CYREG_SFLASH_IMO_TCTRIM_LT22 0x0ffff362u
#define CYREG_SFLASH_IMO_TCTRIM_LT23 0x0ffff363u
#define CYREG_SFLASH_IMO_TCTRIM_LT24 0x0ffff364u
#define CYREG_SFLASH_IMO_TRIM_LT0 0x0ffff365u
#define CYFLD_SFLASH_OFFSET__OFFSET 0x00000000u
#define CYFLD_SFLASH_OFFSET__SIZE 0x00000008u
#define CYREG_SFLASH_IMO_TRIM_LT1 0x0ffff366u
#define CYREG_SFLASH_IMO_TRIM_LT2 0x0ffff367u
#define CYREG_SFLASH_IMO_TRIM_LT3 0x0ffff368u
#define CYREG_SFLASH_IMO_TRIM_LT4 0x0ffff369u
#define CYREG_SFLASH_IMO_TRIM_LT5 0x0ffff36au
#define CYREG_SFLASH_IMO_TRIM_LT6 0x0ffff36bu
#define CYREG_SFLASH_IMO_TRIM_LT7 0x0ffff36cu
#define CYREG_SFLASH_IMO_TRIM_LT8 0x0ffff36du
#define CYREG_SFLASH_IMO_TRIM_LT9 0x0ffff36eu
#define CYREG_SFLASH_IMO_TRIM_LT10 0x0ffff36fu
#define CYREG_SFLASH_IMO_TRIM_LT11 0x0ffff370u
#define CYREG_SFLASH_IMO_TRIM_LT12 0x0ffff371u
#define CYREG_SFLASH_IMO_TRIM_LT13 0x0ffff372u
#define CYREG_SFLASH_IMO_TRIM_LT14 0x0ffff373u
#define CYREG_SFLASH_IMO_TRIM_LT15 0x0ffff374u
#define CYREG_SFLASH_IMO_TRIM_LT16 0x0ffff375u
#define CYREG_SFLASH_IMO_TRIM_LT17 0x0ffff376u
#define CYREG_SFLASH_IMO_TRIM_LT18 0x0ffff377u
#define CYREG_SFLASH_IMO_TRIM_LT19 0x0ffff378u
#define CYREG_SFLASH_IMO_TRIM_LT20 0x0ffff379u
#define CYREG_SFLASH_IMO_TRIM_LT21 0x0ffff37au
#define CYREG_SFLASH_IMO_TRIM_LT22 0x0ffff37bu
#define CYREG_SFLASH_IMO_TRIM_LT23 0x0ffff37cu
#define CYREG_SFLASH_IMO_TRIM_LT24 0x0ffff37du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH0 0x0ffff400u
#define CYFLD_SFLASH_BYTE_MEM__OFFSET 0x00000000u
#define CYFLD_SFLASH_BYTE_MEM__SIZE 0x00000008u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1 0x0ffff401u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH2 0x0ffff402u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH3 0x0ffff403u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH4 0x0ffff404u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH5 0x0ffff405u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH6 0x0ffff406u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH7 0x0ffff407u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH8 0x0ffff408u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH9 0x0ffff409u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH10 0x0ffff40au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH11 0x0ffff40bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH12 0x0ffff40cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH13 0x0ffff40du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH14 0x0ffff40eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH15 0x0ffff40fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH16 0x0ffff410u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH17 0x0ffff411u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH18 0x0ffff412u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH19 0x0ffff413u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH20 0x0ffff414u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH21 0x0ffff415u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH22 0x0ffff416u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH23 0x0ffff417u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH24 0x0ffff418u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH25 0x0ffff419u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH26 0x0ffff41au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH27 0x0ffff41bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH28 0x0ffff41cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH29 0x0ffff41du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH30 0x0ffff41eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH31 0x0ffff41fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH32 0x0ffff420u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH33 0x0ffff421u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH34 0x0ffff422u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH35 0x0ffff423u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH36 0x0ffff424u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH37 0x0ffff425u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH38 0x0ffff426u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH39 0x0ffff427u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH40 0x0ffff428u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH41 0x0ffff429u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH42 0x0ffff42au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH43 0x0ffff42bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH44 0x0ffff42cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH45 0x0ffff42du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH46 0x0ffff42eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH47 0x0ffff42fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH48 0x0ffff430u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH49 0x0ffff431u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH50 0x0ffff432u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH51 0x0ffff433u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH52 0x0ffff434u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH53 0x0ffff435u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH54 0x0ffff436u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH55 0x0ffff437u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH56 0x0ffff438u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH57 0x0ffff439u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH58 0x0ffff43au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH59 0x0ffff43bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH60 0x0ffff43cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH61 0x0ffff43du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH62 0x0ffff43eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH63 0x0ffff43fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH64 0x0ffff440u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH65 0x0ffff441u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH66 0x0ffff442u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH67 0x0ffff443u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH68 0x0ffff444u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH69 0x0ffff445u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH70 0x0ffff446u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH71 0x0ffff447u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH72 0x0ffff448u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH73 0x0ffff449u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH74 0x0ffff44au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH75 0x0ffff44bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH76 0x0ffff44cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH77 0x0ffff44du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH78 0x0ffff44eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH79 0x0ffff44fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH80 0x0ffff450u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH81 0x0ffff451u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH82 0x0ffff452u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH83 0x0ffff453u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH84 0x0ffff454u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH85 0x0ffff455u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH86 0x0ffff456u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH87 0x0ffff457u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH88 0x0ffff458u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH89 0x0ffff459u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH90 0x0ffff45au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH91 0x0ffff45bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH92 0x0ffff45cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH93 0x0ffff45du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH94 0x0ffff45eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH95 0x0ffff45fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH96 0x0ffff460u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH97 0x0ffff461u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH98 0x0ffff462u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH99 0x0ffff463u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH100 0x0ffff464u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH101 0x0ffff465u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH102 0x0ffff466u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH103 0x0ffff467u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH104 0x0ffff468u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH105 0x0ffff469u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH106 0x0ffff46au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH107 0x0ffff46bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH108 0x0ffff46cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH109 0x0ffff46du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH110 0x0ffff46eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH111 0x0ffff46fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH112 0x0ffff470u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH113 0x0ffff471u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH114 0x0ffff472u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH115 0x0ffff473u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH116 0x0ffff474u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH117 0x0ffff475u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH118 0x0ffff476u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH119 0x0ffff477u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH120 0x0ffff478u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH121 0x0ffff479u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH122 0x0ffff47au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH123 0x0ffff47bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH124 0x0ffff47cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH125 0x0ffff47du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH126 0x0ffff47eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH127 0x0ffff47fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH128 0x0ffff480u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH129 0x0ffff481u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH130 0x0ffff482u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH131 0x0ffff483u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH132 0x0ffff484u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH133 0x0ffff485u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH134 0x0ffff486u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH135 0x0ffff487u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH136 0x0ffff488u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH137 0x0ffff489u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH138 0x0ffff48au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH139 0x0ffff48bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH140 0x0ffff48cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH141 0x0ffff48du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH142 0x0ffff48eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH143 0x0ffff48fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH144 0x0ffff490u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH145 0x0ffff491u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH146 0x0ffff492u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH147 0x0ffff493u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH148 0x0ffff494u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH149 0x0ffff495u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH150 0x0ffff496u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH151 0x0ffff497u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH152 0x0ffff498u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH153 0x0ffff499u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH154 0x0ffff49au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH155 0x0ffff49bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH156 0x0ffff49cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH157 0x0ffff49du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH158 0x0ffff49eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH159 0x0ffff49fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH160 0x0ffff4a0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH161 0x0ffff4a1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH162 0x0ffff4a2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH163 0x0ffff4a3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH164 0x0ffff4a4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH165 0x0ffff4a5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH166 0x0ffff4a6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH167 0x0ffff4a7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH168 0x0ffff4a8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH169 0x0ffff4a9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH170 0x0ffff4aau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH171 0x0ffff4abu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH172 0x0ffff4acu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH173 0x0ffff4adu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH174 0x0ffff4aeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH175 0x0ffff4afu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH176 0x0ffff4b0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH177 0x0ffff4b1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH178 0x0ffff4b2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH179 0x0ffff4b3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH180 0x0ffff4b4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH181 0x0ffff4b5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH182 0x0ffff4b6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH183 0x0ffff4b7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH184 0x0ffff4b8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH185 0x0ffff4b9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH186 0x0ffff4bau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH187 0x0ffff4bbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH188 0x0ffff4bcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH189 0x0ffff4bdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH190 0x0ffff4beu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH191 0x0ffff4bfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH192 0x0ffff4c0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH193 0x0ffff4c1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH194 0x0ffff4c2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH195 0x0ffff4c3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH196 0x0ffff4c4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH197 0x0ffff4c5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH198 0x0ffff4c6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH199 0x0ffff4c7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH200 0x0ffff4c8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH201 0x0ffff4c9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH202 0x0ffff4cau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH203 0x0ffff4cbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH204 0x0ffff4ccu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH205 0x0ffff4cdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH206 0x0ffff4ceu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH207 0x0ffff4cfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH208 0x0ffff4d0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH209 0x0ffff4d1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH210 0x0ffff4d2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH211 0x0ffff4d3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH212 0x0ffff4d4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH213 0x0ffff4d5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH214 0x0ffff4d6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH215 0x0ffff4d7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH216 0x0ffff4d8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH217 0x0ffff4d9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH218 0x0ffff4dau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH219 0x0ffff4dbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH220 0x0ffff4dcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH221 0x0ffff4ddu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH222 0x0ffff4deu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH223 0x0ffff4dfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH224 0x0ffff4e0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH225 0x0ffff4e1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH226 0x0ffff4e2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH227 0x0ffff4e3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH228 0x0ffff4e4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH229 0x0ffff4e5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH230 0x0ffff4e6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH231 0x0ffff4e7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH232 0x0ffff4e8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH233 0x0ffff4e9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH234 0x0ffff4eau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH235 0x0ffff4ebu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH236 0x0ffff4ecu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH237 0x0ffff4edu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH238 0x0ffff4eeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH239 0x0ffff4efu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH240 0x0ffff4f0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH241 0x0ffff4f1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH242 0x0ffff4f2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH243 0x0ffff4f3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH244 0x0ffff4f4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH245 0x0ffff4f5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH246 0x0ffff4f6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH247 0x0ffff4f7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH248 0x0ffff4f8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH249 0x0ffff4f9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH250 0x0ffff4fau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH251 0x0ffff4fbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH252 0x0ffff4fcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH253 0x0ffff4fdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH254 0x0ffff4feu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH255 0x0ffff4ffu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH256 0x0ffff500u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH257 0x0ffff501u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH258 0x0ffff502u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH259 0x0ffff503u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH260 0x0ffff504u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH261 0x0ffff505u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH262 0x0ffff506u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH263 0x0ffff507u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH264 0x0ffff508u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH265 0x0ffff509u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH266 0x0ffff50au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH267 0x0ffff50bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH268 0x0ffff50cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH269 0x0ffff50du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH270 0x0ffff50eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH271 0x0ffff50fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH272 0x0ffff510u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH273 0x0ffff511u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH274 0x0ffff512u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH275 0x0ffff513u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH276 0x0ffff514u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH277 0x0ffff515u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH278 0x0ffff516u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH279 0x0ffff517u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH280 0x0ffff518u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH281 0x0ffff519u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH282 0x0ffff51au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH283 0x0ffff51bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH284 0x0ffff51cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH285 0x0ffff51du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH286 0x0ffff51eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH287 0x0ffff51fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH288 0x0ffff520u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH289 0x0ffff521u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH290 0x0ffff522u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH291 0x0ffff523u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH292 0x0ffff524u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH293 0x0ffff525u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH294 0x0ffff526u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH295 0x0ffff527u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH296 0x0ffff528u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH297 0x0ffff529u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH298 0x0ffff52au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH299 0x0ffff52bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH300 0x0ffff52cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH301 0x0ffff52du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH302 0x0ffff52eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH303 0x0ffff52fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH304 0x0ffff530u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH305 0x0ffff531u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH306 0x0ffff532u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH307 0x0ffff533u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH308 0x0ffff534u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH309 0x0ffff535u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH310 0x0ffff536u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH311 0x0ffff537u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH312 0x0ffff538u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH313 0x0ffff539u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH314 0x0ffff53au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH315 0x0ffff53bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH316 0x0ffff53cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH317 0x0ffff53du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH318 0x0ffff53eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH319 0x0ffff53fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH320 0x0ffff540u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH321 0x0ffff541u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH322 0x0ffff542u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH323 0x0ffff543u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH324 0x0ffff544u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH325 0x0ffff545u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH326 0x0ffff546u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH327 0x0ffff547u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH328 0x0ffff548u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH329 0x0ffff549u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH330 0x0ffff54au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH331 0x0ffff54bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH332 0x0ffff54cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH333 0x0ffff54du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH334 0x0ffff54eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH335 0x0ffff54fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH336 0x0ffff550u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH337 0x0ffff551u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH338 0x0ffff552u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH339 0x0ffff553u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH340 0x0ffff554u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH341 0x0ffff555u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH342 0x0ffff556u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH343 0x0ffff557u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH344 0x0ffff558u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH345 0x0ffff559u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH346 0x0ffff55au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH347 0x0ffff55bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH348 0x0ffff55cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH349 0x0ffff55du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH350 0x0ffff55eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH351 0x0ffff55fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH352 0x0ffff560u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH353 0x0ffff561u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH354 0x0ffff562u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH355 0x0ffff563u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH356 0x0ffff564u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH357 0x0ffff565u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH358 0x0ffff566u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH359 0x0ffff567u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH360 0x0ffff568u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH361 0x0ffff569u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH362 0x0ffff56au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH363 0x0ffff56bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH364 0x0ffff56cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH365 0x0ffff56du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH366 0x0ffff56eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH367 0x0ffff56fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH368 0x0ffff570u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH369 0x0ffff571u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH370 0x0ffff572u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH371 0x0ffff573u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH372 0x0ffff574u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH373 0x0ffff575u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH374 0x0ffff576u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH375 0x0ffff577u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH376 0x0ffff578u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH377 0x0ffff579u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH378 0x0ffff57au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH379 0x0ffff57bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH380 0x0ffff57cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH381 0x0ffff57du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH382 0x0ffff57eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH383 0x0ffff57fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH384 0x0ffff580u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH385 0x0ffff581u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH386 0x0ffff582u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH387 0x0ffff583u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH388 0x0ffff584u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH389 0x0ffff585u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH390 0x0ffff586u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH391 0x0ffff587u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH392 0x0ffff588u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH393 0x0ffff589u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH394 0x0ffff58au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH395 0x0ffff58bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH396 0x0ffff58cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH397 0x0ffff58du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH398 0x0ffff58eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH399 0x0ffff58fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH400 0x0ffff590u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH401 0x0ffff591u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH402 0x0ffff592u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH403 0x0ffff593u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH404 0x0ffff594u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH405 0x0ffff595u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH406 0x0ffff596u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH407 0x0ffff597u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH408 0x0ffff598u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH409 0x0ffff599u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH410 0x0ffff59au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH411 0x0ffff59bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH412 0x0ffff59cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH413 0x0ffff59du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH414 0x0ffff59eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH415 0x0ffff59fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH416 0x0ffff5a0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH417 0x0ffff5a1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH418 0x0ffff5a2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH419 0x0ffff5a3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH420 0x0ffff5a4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH421 0x0ffff5a5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH422 0x0ffff5a6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH423 0x0ffff5a7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH424 0x0ffff5a8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH425 0x0ffff5a9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH426 0x0ffff5aau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH427 0x0ffff5abu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH428 0x0ffff5acu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH429 0x0ffff5adu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH430 0x0ffff5aeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH431 0x0ffff5afu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH432 0x0ffff5b0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH433 0x0ffff5b1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH434 0x0ffff5b2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH435 0x0ffff5b3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH436 0x0ffff5b4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH437 0x0ffff5b5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH438 0x0ffff5b6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH439 0x0ffff5b7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH440 0x0ffff5b8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH441 0x0ffff5b9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH442 0x0ffff5bau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH443 0x0ffff5bbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH444 0x0ffff5bcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH445 0x0ffff5bdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH446 0x0ffff5beu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH447 0x0ffff5bfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH448 0x0ffff5c0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH449 0x0ffff5c1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH450 0x0ffff5c2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH451 0x0ffff5c3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH452 0x0ffff5c4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH453 0x0ffff5c5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH454 0x0ffff5c6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH455 0x0ffff5c7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH456 0x0ffff5c8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH457 0x0ffff5c9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH458 0x0ffff5cau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH459 0x0ffff5cbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH460 0x0ffff5ccu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH461 0x0ffff5cdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH462 0x0ffff5ceu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH463 0x0ffff5cfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH464 0x0ffff5d0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH465 0x0ffff5d1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH466 0x0ffff5d2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH467 0x0ffff5d3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH468 0x0ffff5d4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH469 0x0ffff5d5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH470 0x0ffff5d6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH471 0x0ffff5d7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH472 0x0ffff5d8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH473 0x0ffff5d9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH474 0x0ffff5dau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH475 0x0ffff5dbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH476 0x0ffff5dcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH477 0x0ffff5ddu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH478 0x0ffff5deu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH479 0x0ffff5dfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH480 0x0ffff5e0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH481 0x0ffff5e1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH482 0x0ffff5e2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH483 0x0ffff5e3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH484 0x0ffff5e4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH485 0x0ffff5e5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH486 0x0ffff5e6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH487 0x0ffff5e7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH488 0x0ffff5e8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH489 0x0ffff5e9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH490 0x0ffff5eau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH491 0x0ffff5ebu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH492 0x0ffff5ecu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH493 0x0ffff5edu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH494 0x0ffff5eeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH495 0x0ffff5efu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH496 0x0ffff5f0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH497 0x0ffff5f1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH498 0x0ffff5f2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH499 0x0ffff5f3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH500 0x0ffff5f4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH501 0x0ffff5f5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH502 0x0ffff5f6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH503 0x0ffff5f7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH504 0x0ffff5f8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH505 0x0ffff5f9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH506 0x0ffff5fau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH507 0x0ffff5fbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH508 0x0ffff5fcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH509 0x0ffff5fdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH510 0x0ffff5feu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH511 0x0ffff5ffu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH512 0x0ffff600u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH513 0x0ffff601u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH514 0x0ffff602u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH515 0x0ffff603u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH516 0x0ffff604u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH517 0x0ffff605u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH518 0x0ffff606u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH519 0x0ffff607u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH520 0x0ffff608u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH521 0x0ffff609u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH522 0x0ffff60au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH523 0x0ffff60bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH524 0x0ffff60cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH525 0x0ffff60du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH526 0x0ffff60eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH527 0x0ffff60fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH528 0x0ffff610u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH529 0x0ffff611u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH530 0x0ffff612u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH531 0x0ffff613u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH532 0x0ffff614u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH533 0x0ffff615u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH534 0x0ffff616u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH535 0x0ffff617u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH536 0x0ffff618u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH537 0x0ffff619u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH538 0x0ffff61au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH539 0x0ffff61bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH540 0x0ffff61cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH541 0x0ffff61du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH542 0x0ffff61eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH543 0x0ffff61fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH544 0x0ffff620u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH545 0x0ffff621u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH546 0x0ffff622u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH547 0x0ffff623u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH548 0x0ffff624u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH549 0x0ffff625u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH550 0x0ffff626u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH551 0x0ffff627u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH552 0x0ffff628u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH553 0x0ffff629u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH554 0x0ffff62au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH555 0x0ffff62bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH556 0x0ffff62cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH557 0x0ffff62du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH558 0x0ffff62eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH559 0x0ffff62fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH560 0x0ffff630u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH561 0x0ffff631u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH562 0x0ffff632u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH563 0x0ffff633u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH564 0x0ffff634u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH565 0x0ffff635u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH566 0x0ffff636u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH567 0x0ffff637u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH568 0x0ffff638u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH569 0x0ffff639u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH570 0x0ffff63au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH571 0x0ffff63bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH572 0x0ffff63cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH573 0x0ffff63du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH574 0x0ffff63eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH575 0x0ffff63fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH576 0x0ffff640u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH577 0x0ffff641u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH578 0x0ffff642u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH579 0x0ffff643u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH580 0x0ffff644u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH581 0x0ffff645u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH582 0x0ffff646u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH583 0x0ffff647u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH584 0x0ffff648u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH585 0x0ffff649u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH586 0x0ffff64au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH587 0x0ffff64bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH588 0x0ffff64cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH589 0x0ffff64du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH590 0x0ffff64eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH591 0x0ffff64fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH592 0x0ffff650u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH593 0x0ffff651u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH594 0x0ffff652u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH595 0x0ffff653u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH596 0x0ffff654u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH597 0x0ffff655u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH598 0x0ffff656u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH599 0x0ffff657u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH600 0x0ffff658u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH601 0x0ffff659u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH602 0x0ffff65au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH603 0x0ffff65bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH604 0x0ffff65cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH605 0x0ffff65du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH606 0x0ffff65eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH607 0x0ffff65fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH608 0x0ffff660u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH609 0x0ffff661u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH610 0x0ffff662u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH611 0x0ffff663u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH612 0x0ffff664u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH613 0x0ffff665u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH614 0x0ffff666u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH615 0x0ffff667u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH616 0x0ffff668u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH617 0x0ffff669u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH618 0x0ffff66au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH619 0x0ffff66bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH620 0x0ffff66cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH621 0x0ffff66du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH622 0x0ffff66eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH623 0x0ffff66fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH624 0x0ffff670u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH625 0x0ffff671u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH626 0x0ffff672u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH627 0x0ffff673u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH628 0x0ffff674u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH629 0x0ffff675u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH630 0x0ffff676u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH631 0x0ffff677u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH632 0x0ffff678u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH633 0x0ffff679u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH634 0x0ffff67au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH635 0x0ffff67bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH636 0x0ffff67cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH637 0x0ffff67du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH638 0x0ffff67eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH639 0x0ffff67fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH640 0x0ffff680u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH641 0x0ffff681u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH642 0x0ffff682u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH643 0x0ffff683u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH644 0x0ffff684u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH645 0x0ffff685u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH646 0x0ffff686u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH647 0x0ffff687u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH648 0x0ffff688u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH649 0x0ffff689u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH650 0x0ffff68au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH651 0x0ffff68bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH652 0x0ffff68cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH653 0x0ffff68du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH654 0x0ffff68eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH655 0x0ffff68fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH656 0x0ffff690u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH657 0x0ffff691u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH658 0x0ffff692u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH659 0x0ffff693u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH660 0x0ffff694u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH661 0x0ffff695u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH662 0x0ffff696u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH663 0x0ffff697u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH664 0x0ffff698u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH665 0x0ffff699u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH666 0x0ffff69au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH667 0x0ffff69bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH668 0x0ffff69cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH669 0x0ffff69du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH670 0x0ffff69eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH671 0x0ffff69fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH672 0x0ffff6a0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH673 0x0ffff6a1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH674 0x0ffff6a2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH675 0x0ffff6a3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH676 0x0ffff6a4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH677 0x0ffff6a5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH678 0x0ffff6a6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH679 0x0ffff6a7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH680 0x0ffff6a8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH681 0x0ffff6a9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH682 0x0ffff6aau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH683 0x0ffff6abu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH684 0x0ffff6acu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH685 0x0ffff6adu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH686 0x0ffff6aeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH687 0x0ffff6afu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH688 0x0ffff6b0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH689 0x0ffff6b1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH690 0x0ffff6b2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH691 0x0ffff6b3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH692 0x0ffff6b4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH693 0x0ffff6b5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH694 0x0ffff6b6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH695 0x0ffff6b7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH696 0x0ffff6b8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH697 0x0ffff6b9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH698 0x0ffff6bau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH699 0x0ffff6bbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH700 0x0ffff6bcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH701 0x0ffff6bdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH702 0x0ffff6beu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH703 0x0ffff6bfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH704 0x0ffff6c0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH705 0x0ffff6c1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH706 0x0ffff6c2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH707 0x0ffff6c3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH708 0x0ffff6c4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH709 0x0ffff6c5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH710 0x0ffff6c6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH711 0x0ffff6c7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH712 0x0ffff6c8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH713 0x0ffff6c9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH714 0x0ffff6cau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH715 0x0ffff6cbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH716 0x0ffff6ccu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH717 0x0ffff6cdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH718 0x0ffff6ceu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH719 0x0ffff6cfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH720 0x0ffff6d0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH721 0x0ffff6d1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH722 0x0ffff6d2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH723 0x0ffff6d3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH724 0x0ffff6d4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH725 0x0ffff6d5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH726 0x0ffff6d6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH727 0x0ffff6d7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH728 0x0ffff6d8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH729 0x0ffff6d9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH730 0x0ffff6dau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH731 0x0ffff6dbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH732 0x0ffff6dcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH733 0x0ffff6ddu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH734 0x0ffff6deu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH735 0x0ffff6dfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH736 0x0ffff6e0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH737 0x0ffff6e1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH738 0x0ffff6e2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH739 0x0ffff6e3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH740 0x0ffff6e4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH741 0x0ffff6e5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH742 0x0ffff6e6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH743 0x0ffff6e7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH744 0x0ffff6e8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH745 0x0ffff6e9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH746 0x0ffff6eau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH747 0x0ffff6ebu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH748 0x0ffff6ecu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH749 0x0ffff6edu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH750 0x0ffff6eeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH751 0x0ffff6efu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH752 0x0ffff6f0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH753 0x0ffff6f1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH754 0x0ffff6f2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH755 0x0ffff6f3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH756 0x0ffff6f4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH757 0x0ffff6f5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH758 0x0ffff6f6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH759 0x0ffff6f7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH760 0x0ffff6f8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH761 0x0ffff6f9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH762 0x0ffff6fau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH763 0x0ffff6fbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH764 0x0ffff6fcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH765 0x0ffff6fdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH766 0x0ffff6feu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH767 0x0ffff6ffu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH768 0x0ffff700u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH769 0x0ffff701u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH770 0x0ffff702u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH771 0x0ffff703u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH772 0x0ffff704u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH773 0x0ffff705u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH774 0x0ffff706u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH775 0x0ffff707u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH776 0x0ffff708u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH777 0x0ffff709u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH778 0x0ffff70au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH779 0x0ffff70bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH780 0x0ffff70cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH781 0x0ffff70du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH782 0x0ffff70eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH783 0x0ffff70fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH784 0x0ffff710u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH785 0x0ffff711u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH786 0x0ffff712u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH787 0x0ffff713u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH788 0x0ffff714u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH789 0x0ffff715u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH790 0x0ffff716u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH791 0x0ffff717u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH792 0x0ffff718u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH793 0x0ffff719u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH794 0x0ffff71au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH795 0x0ffff71bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH796 0x0ffff71cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH797 0x0ffff71du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH798 0x0ffff71eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH799 0x0ffff71fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH800 0x0ffff720u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH801 0x0ffff721u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH802 0x0ffff722u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH803 0x0ffff723u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH804 0x0ffff724u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH805 0x0ffff725u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH806 0x0ffff726u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH807 0x0ffff727u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH808 0x0ffff728u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH809 0x0ffff729u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH810 0x0ffff72au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH811 0x0ffff72bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH812 0x0ffff72cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH813 0x0ffff72du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH814 0x0ffff72eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH815 0x0ffff72fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH816 0x0ffff730u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH817 0x0ffff731u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH818 0x0ffff732u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH819 0x0ffff733u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH820 0x0ffff734u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH821 0x0ffff735u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH822 0x0ffff736u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH823 0x0ffff737u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH824 0x0ffff738u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH825 0x0ffff739u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH826 0x0ffff73au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH827 0x0ffff73bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH828 0x0ffff73cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH829 0x0ffff73du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH830 0x0ffff73eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH831 0x0ffff73fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH832 0x0ffff740u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH833 0x0ffff741u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH834 0x0ffff742u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH835 0x0ffff743u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH836 0x0ffff744u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH837 0x0ffff745u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH838 0x0ffff746u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH839 0x0ffff747u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH840 0x0ffff748u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH841 0x0ffff749u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH842 0x0ffff74au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH843 0x0ffff74bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH844 0x0ffff74cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH845 0x0ffff74du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH846 0x0ffff74eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH847 0x0ffff74fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH848 0x0ffff750u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH849 0x0ffff751u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH850 0x0ffff752u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH851 0x0ffff753u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH852 0x0ffff754u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH853 0x0ffff755u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH854 0x0ffff756u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH855 0x0ffff757u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH856 0x0ffff758u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH857 0x0ffff759u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH858 0x0ffff75au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH859 0x0ffff75bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH860 0x0ffff75cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH861 0x0ffff75du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH862 0x0ffff75eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH863 0x0ffff75fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH864 0x0ffff760u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH865 0x0ffff761u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH866 0x0ffff762u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH867 0x0ffff763u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH868 0x0ffff764u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH869 0x0ffff765u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH870 0x0ffff766u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH871 0x0ffff767u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH872 0x0ffff768u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH873 0x0ffff769u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH874 0x0ffff76au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH875 0x0ffff76bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH876 0x0ffff76cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH877 0x0ffff76du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH878 0x0ffff76eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH879 0x0ffff76fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH880 0x0ffff770u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH881 0x0ffff771u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH882 0x0ffff772u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH883 0x0ffff773u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH884 0x0ffff774u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH885 0x0ffff775u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH886 0x0ffff776u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH887 0x0ffff777u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH888 0x0ffff778u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH889 0x0ffff779u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH890 0x0ffff77au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH891 0x0ffff77bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH892 0x0ffff77cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH893 0x0ffff77du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH894 0x0ffff77eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH895 0x0ffff77fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH896 0x0ffff780u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH897 0x0ffff781u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH898 0x0ffff782u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH899 0x0ffff783u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH900 0x0ffff784u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH901 0x0ffff785u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH902 0x0ffff786u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH903 0x0ffff787u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH904 0x0ffff788u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH905 0x0ffff789u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH906 0x0ffff78au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH907 0x0ffff78bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH908 0x0ffff78cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH909 0x0ffff78du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH910 0x0ffff78eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH911 0x0ffff78fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH912 0x0ffff790u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH913 0x0ffff791u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH914 0x0ffff792u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH915 0x0ffff793u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH916 0x0ffff794u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH917 0x0ffff795u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH918 0x0ffff796u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH919 0x0ffff797u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH920 0x0ffff798u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH921 0x0ffff799u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH922 0x0ffff79au
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH923 0x0ffff79bu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH924 0x0ffff79cu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH925 0x0ffff79du
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH926 0x0ffff79eu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH927 0x0ffff79fu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH928 0x0ffff7a0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH929 0x0ffff7a1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH930 0x0ffff7a2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH931 0x0ffff7a3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH932 0x0ffff7a4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH933 0x0ffff7a5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH934 0x0ffff7a6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH935 0x0ffff7a7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH936 0x0ffff7a8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH937 0x0ffff7a9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH938 0x0ffff7aau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH939 0x0ffff7abu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH940 0x0ffff7acu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH941 0x0ffff7adu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH942 0x0ffff7aeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH943 0x0ffff7afu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH944 0x0ffff7b0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH945 0x0ffff7b1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH946 0x0ffff7b2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH947 0x0ffff7b3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH948 0x0ffff7b4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH949 0x0ffff7b5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH950 0x0ffff7b6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH951 0x0ffff7b7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH952 0x0ffff7b8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH953 0x0ffff7b9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH954 0x0ffff7bau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH955 0x0ffff7bbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH956 0x0ffff7bcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH957 0x0ffff7bdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH958 0x0ffff7beu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH959 0x0ffff7bfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH960 0x0ffff7c0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH961 0x0ffff7c1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH962 0x0ffff7c2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH963 0x0ffff7c3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH964 0x0ffff7c4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH965 0x0ffff7c5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH966 0x0ffff7c6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH967 0x0ffff7c7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH968 0x0ffff7c8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH969 0x0ffff7c9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH970 0x0ffff7cau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH971 0x0ffff7cbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH972 0x0ffff7ccu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH973 0x0ffff7cdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH974 0x0ffff7ceu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH975 0x0ffff7cfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH976 0x0ffff7d0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH977 0x0ffff7d1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH978 0x0ffff7d2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH979 0x0ffff7d3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH980 0x0ffff7d4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH981 0x0ffff7d5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH982 0x0ffff7d6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH983 0x0ffff7d7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH984 0x0ffff7d8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH985 0x0ffff7d9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH986 0x0ffff7dau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH987 0x0ffff7dbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH988 0x0ffff7dcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH989 0x0ffff7ddu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH990 0x0ffff7deu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH991 0x0ffff7dfu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH992 0x0ffff7e0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH993 0x0ffff7e1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH994 0x0ffff7e2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH995 0x0ffff7e3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH996 0x0ffff7e4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH997 0x0ffff7e5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH998 0x0ffff7e6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH999 0x0ffff7e7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1000 0x0ffff7e8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1001 0x0ffff7e9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1002 0x0ffff7eau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1003 0x0ffff7ebu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1004 0x0ffff7ecu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1005 0x0ffff7edu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1006 0x0ffff7eeu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1007 0x0ffff7efu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1008 0x0ffff7f0u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1009 0x0ffff7f1u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1010 0x0ffff7f2u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1011 0x0ffff7f3u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1012 0x0ffff7f4u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1013 0x0ffff7f5u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1014 0x0ffff7f6u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1015 0x0ffff7f7u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1016 0x0ffff7f8u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1017 0x0ffff7f9u
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1018 0x0ffff7fau
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1019 0x0ffff7fbu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1020 0x0ffff7fcu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1021 0x0ffff7fdu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1022 0x0ffff7feu
#define CYREG_SFLASH_MACRO_0_FREE_SFLASH1023 0x0ffff7ffu
#define CYDEV_ROM_BASE 0x10000000u
#define CYDEV_ROM_SIZE 0x00002000u
#define CYREG_ROM_DATA_MBASE 0x10000000u
#define CYREG_ROM_DATA_MSIZE 0x00002000u
#define CYDEV_SRAM_BASE 0x20000000u
#define CYDEV_SRAM_SIZE 0x00004000u
#define CYREG_SRAM_DATA_MBASE 0x20000000u
#define CYREG_SRAM_DATA_MSIZE 0x00004000u
#define CYDEV_PERI_BASE 0x40010000u
#define CYDEV_PERI_SIZE 0x00010000u
#define CYREG_PERI_DIV_CMD 0x40010000u
#define CYFLD_PERI_SEL_DIV__OFFSET 0x00000000u
#define CYFLD_PERI_SEL_DIV__SIZE 0x00000006u
#define CYFLD_PERI_SEL_TYPE__OFFSET 0x00000006u
#define CYFLD_PERI_SEL_TYPE__SIZE 0x00000002u
#define CYFLD_PERI_PA_SEL_DIV__OFFSET 0x00000008u
#define CYFLD_PERI_PA_SEL_DIV__SIZE 0x00000006u
#define CYFLD_PERI_PA_SEL_TYPE__OFFSET 0x0000000eu
#define CYFLD_PERI_PA_SEL_TYPE__SIZE 0x00000002u
#define CYFLD_PERI_DISABLE__OFFSET 0x0000001eu
#define CYFLD_PERI_DISABLE__SIZE 0x00000001u
#define CYFLD_PERI_ENABLE__OFFSET 0x0000001fu
#define CYFLD_PERI_ENABLE__SIZE 0x00000001u
#define CYREG_PERI_PCLK_CTL0 0x40010100u
/* Duplicate field name in PERI: SEL_DIV [3:0] (previous: [5:0]) */
#define CYREG_PERI_PCLK_CTL1 0x40010104u
#define CYREG_PERI_PCLK_CTL2 0x40010108u
#define CYREG_PERI_PCLK_CTL3 0x4001010cu
#define CYREG_PERI_PCLK_CTL4 0x40010110u
#define CYREG_PERI_PCLK_CTL5 0x40010114u
#define CYREG_PERI_PCLK_CTL6 0x40010118u
#define CYREG_PERI_PCLK_CTL7 0x4001011cu
#define CYREG_PERI_PCLK_CTL8 0x40010120u
#define CYREG_PERI_PCLK_CTL9 0x40010124u
#define CYREG_PERI_PCLK_CTL10 0x40010128u
#define CYREG_PERI_PCLK_CTL11 0x4001012cu
#define CYREG_PERI_PCLK_CTL12 0x40010130u
#define CYREG_PERI_PCLK_CTL13 0x40010134u
#define CYREG_PERI_PCLK_CTL14 0x40010138u
#define CYREG_PERI_PCLK_CTL15 0x4001013cu
#define CYREG_PERI_PCLK_CTL16 0x40010140u
#define CYREG_PERI_PCLK_CTL17 0x40010144u
#define CYREG_PERI_PCLK_CTL18 0x40010148u
#define CYREG_PERI_DIV_16_CTL0 0x40010300u
#define CYFLD_PERI_EN__OFFSET 0x00000000u
#define CYFLD_PERI_EN__SIZE 0x00000001u
#define CYFLD_PERI_INT16_DIV__OFFSET 0x00000008u
#define CYFLD_PERI_INT16_DIV__SIZE 0x00000010u
#define CYREG_PERI_DIV_16_CTL1 0x40010304u
#define CYREG_PERI_DIV_16_CTL2 0x40010308u
#define CYREG_PERI_DIV_16_CTL3 0x4001030cu
#define CYREG_PERI_DIV_16_CTL4 0x40010310u
#define CYREG_PERI_DIV_16_CTL5 0x40010314u
#define CYREG_PERI_DIV_16_CTL6 0x40010318u
#define CYREG_PERI_DIV_16_CTL7 0x4001031cu
#define CYREG_PERI_DIV_16_CTL8 0x40010320u
#define CYREG_PERI_DIV_16_CTL9 0x40010324u
#define CYREG_PERI_DIV_16_CTL10 0x40010328u
#define CYREG_PERI_DIV_16_CTL11 0x4001032cu
#define CYREG_PERI_DIV_16_5_CTL0 0x40010400u
#define CYFLD_PERI_FRAC5_DIV__OFFSET 0x00000003u
#define CYFLD_PERI_FRAC5_DIV__SIZE 0x00000005u
#define CYREG_PERI_DIV_16_5_CTL1 0x40010404u
#define CYREG_PERI_DIV_16_5_CTL2 0x40010408u
#define CYREG_PERI_DIV_16_5_CTL3 0x4001040cu
#define CYREG_PERI_DIV_16_5_CTL4 0x40010410u
#define CYREG_PERI_DIV_24_5_CTL 0x40010500u
#define CYFLD_PERI_INT24_DIV__OFFSET 0x00000008u
#define CYFLD_PERI_INT24_DIV__SIZE 0x00000018u
#define CYREG_PERI_TR_CTL 0x40010600u
#define CYFLD_PERI_TR_SEL__OFFSET 0x00000000u
#define CYFLD_PERI_TR_SEL__SIZE 0x00000007u
#define CYFLD_PERI_TR_GROUP__OFFSET 0x00000008u
#define CYFLD_PERI_TR_GROUP__SIZE 0x00000004u
#define CYFLD_PERI_TR_COUNT__OFFSET 0x00000010u
#define CYFLD_PERI_TR_COUNT__SIZE 0x00000008u
#define CYFLD_PERI_TR_OUT__OFFSET 0x0000001eu
#define CYFLD_PERI_TR_OUT__SIZE 0x00000001u
#define CYFLD_PERI_TR_ACT__OFFSET 0x0000001fu
#define CYFLD_PERI_TR_ACT__SIZE 0x00000001u
#define CYDEV_PERI_TR_GROUP0_BASE 0x40012000u
#define CYDEV_PERI_TR_GROUP0_SIZE 0x00000200u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL0 0x40012000u
#define CYFLD_PERI_TR_GROUP_SEL__OFFSET 0x00000000u
#define CYFLD_PERI_TR_GROUP_SEL__SIZE 0x00000006u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL1 0x40012004u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL2 0x40012008u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL3 0x4001200cu
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL4 0x40012010u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL5 0x40012014u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL6 0x40012018u
#define CYREG_PERI_TR_GROUP0_TR_OUT_CTL7 0x4001201cu
#define CYDEV_PERI_TR_GROUP1_BASE 0x40012200u
#define CYDEV_PERI_TR_GROUP1_SIZE 0x00000200u
#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL0 0x40012200u
/* Duplicate field name in PERI_TR_GROUP: SEL [4:0] (previous: [5:0]) */
#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL1 0x40012204u
#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL2 0x40012208u
#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL3 0x4001220cu
#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL4 0x40012210u
#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL5 0x40012214u
#define CYREG_PERI_TR_GROUP1_TR_OUT_CTL6 0x40012218u
#define CYDEV_PERI_TR_GROUP2_BASE 0x40012400u
#define CYDEV_PERI_TR_GROUP2_SIZE 0x00000200u
#define CYREG_PERI_TR_GROUP2_TR_OUT_CTL 0x40012400u
/* Duplicate field name in PERI_TR_GROUP: SEL [5:0] (previous: [4:0]) */
#define CYDEV_PERI_TR_GROUP3_BASE 0x40012600u
#define CYDEV_PERI_TR_GROUP3_SIZE 0x00000200u
#define CYREG_PERI_TR_GROUP3_TR_OUT_CTL 0x40012600u
/* Duplicate field name in PERI_TR_GROUP: SEL [3:0] (previous: [5:0]) */
#define CYDEV_HSIOM_BASE 0x40020000u
#define CYDEV_HSIOM_SIZE 0x00004000u
#define CYREG_HSIOM_PORT_SEL0 0x40020000u
#define CYFLD_HSIOM_IO0_SEL__OFFSET 0x00000000u
#define CYFLD_HSIOM_IO0_SEL__SIZE 0x00000004u
#define CYVAL_HSIOM_IO0_SEL_GPIO 0x00000000u
#define CYVAL_HSIOM_IO0_SEL_GPIO_DSI 0x00000001u
#define CYVAL_HSIOM_IO0_SEL_DSI_DSI 0x00000002u
#define CYVAL_HSIOM_IO0_SEL_DSI_GPIO 0x00000003u
#define CYVAL_HSIOM_IO0_SEL_CSD_SENSE 0x00000004u
#define CYVAL_HSIOM_IO0_SEL_CSD_SHIELD 0x00000005u
#define CYVAL_HSIOM_IO0_SEL_AMUXA 0x00000006u
#define CYVAL_HSIOM_IO0_SEL_AMUXB 0x00000007u
#define CYVAL_HSIOM_IO0_SEL_ACT_0 0x00000008u
#define CYVAL_HSIOM_IO0_SEL_ACT_1 0x00000009u
#define CYVAL_HSIOM_IO0_SEL_ACT_2 0x0000000au
#define CYVAL_HSIOM_IO0_SEL_ACT_3 0x0000000bu
#define CYVAL_HSIOM_IO0_SEL_LCD_COM 0x0000000cu
#define CYVAL_HSIOM_IO0_SEL_LCD_SEG 0x0000000du
#define CYVAL_HSIOM_IO0_SEL_DS_0 0x0000000cu
#define CYVAL_HSIOM_IO0_SEL_DS_1 0x0000000du
#define CYVAL_HSIOM_IO0_SEL_DS_2 0x0000000eu
#define CYVAL_HSIOM_IO0_SEL_DS_3 0x0000000fu
#define CYFLD_HSIOM_IO1_SEL__OFFSET 0x00000004u
#define CYFLD_HSIOM_IO1_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO2_SEL__OFFSET 0x00000008u
#define CYFLD_HSIOM_IO2_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO3_SEL__OFFSET 0x0000000cu
#define CYFLD_HSIOM_IO3_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO4_SEL__OFFSET 0x00000010u
#define CYFLD_HSIOM_IO4_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO5_SEL__OFFSET 0x00000014u
#define CYFLD_HSIOM_IO5_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO6_SEL__OFFSET 0x00000018u
#define CYFLD_HSIOM_IO6_SEL__SIZE 0x00000004u
#define CYFLD_HSIOM_IO7_SEL__OFFSET 0x0000001cu
#define CYFLD_HSIOM_IO7_SEL__SIZE 0x00000004u
#define CYREG_HSIOM_PORT_SEL1 0x40020100u
#define CYREG_HSIOM_PORT_SEL2 0x40020200u
#define CYREG_HSIOM_PORT_SEL3 0x40020300u
#define CYREG_HSIOM_PORT_SEL4 0x40020400u
#define CYREG_HSIOM_PORT_SEL5 0x40020500u
#define CYREG_HSIOM_PORT_SEL6 0x40020600u
#define CYREG_HSIOM_PORT_SEL7 0x40020700u
#define CYREG_HSIOM_AMUX_SPLIT_CTL0 0x40022100u
#define CYFLD_HSIOM_SWITCH_AA_SL__OFFSET 0x00000000u
#define CYFLD_HSIOM_SWITCH_AA_SL__SIZE 0x00000001u
#define CYFLD_HSIOM_SWITCH_AA_SR__OFFSET 0x00000001u
#define CYFLD_HSIOM_SWITCH_AA_SR__SIZE 0x00000001u
#define CYFLD_HSIOM_SWITCH_AA_S0__OFFSET 0x00000002u
#define CYFLD_HSIOM_SWITCH_AA_S0__SIZE 0x00000001u
#define CYFLD_HSIOM_SWITCH_BB_SL__OFFSET 0x00000004u
#define CYFLD_HSIOM_SWITCH_BB_SL__SIZE 0x00000001u
#define CYFLD_HSIOM_SWITCH_BB_SR__OFFSET 0x00000005u
#define CYFLD_HSIOM_SWITCH_BB_SR__SIZE 0x00000001u
#define CYFLD_HSIOM_SWITCH_BB_S0__OFFSET 0x00000006u
#define CYFLD_HSIOM_SWITCH_BB_S0__SIZE 0x00000001u
#define CYREG_HSIOM_AMUX_SPLIT_CTL1 0x40022104u
#define CYREG_PWR_CONTROL 0x40030000u
#define CYFLD__POWER_MODE__OFFSET 0x00000000u
#define CYFLD__POWER_MODE__SIZE 0x00000004u
#define CYVAL__POWER_MODE_RESET 0x00000000u
#define CYVAL__POWER_MODE_ACTIVE 0x00000001u
#define CYVAL__POWER_MODE_SLEEP 0x00000002u
#define CYVAL__POWER_MODE_DEEP_SLEEP 0x00000003u
#define CYFLD__DEBUG_SESSION__OFFSET 0x00000004u
#define CYFLD__DEBUG_SESSION__SIZE 0x00000001u
#define CYVAL__DEBUG_SESSION_NO_SESSION 0x00000000u
#define CYVAL__DEBUG_SESSION_SESSION_ACTIVE 0x00000001u
#define CYFLD__LPM_READY__OFFSET 0x00000005u
#define CYFLD__LPM_READY__SIZE 0x00000001u
#define CYFLD__OVER_TEMP_EN__OFFSET 0x00000010u
#define CYFLD__OVER_TEMP_EN__SIZE 0x00000001u
#define CYFLD__OVER_TEMP_THRESH__OFFSET 0x00000011u
#define CYFLD__OVER_TEMP_THRESH__SIZE 0x00000001u
#define CYFLD__SPARE__OFFSET 0x00000012u
#define CYFLD__SPARE__SIZE 0x00000002u
#define CYFLD__EXT_VCCD__OFFSET 0x00000017u
#define CYFLD__EXT_VCCD__SIZE 0x00000001u
#define CYREG_PWR_KEY_DELAY 0x40030004u
#define CYFLD__WAKEUP_HOLDOFF__OFFSET 0x00000000u
#define CYFLD__WAKEUP_HOLDOFF__SIZE 0x0000000au
#define CYREG_PWR_DDFT_SELECT 0x4003000cu
#define CYFLD__DDFT0_SEL__OFFSET 0x00000000u
#define CYFLD__DDFT0_SEL__SIZE 0x00000004u
#define CYVAL__DDFT0_SEL_WAKEUP 0x00000000u
#define CYVAL__DDFT0_SEL_AWAKE 0x00000001u
#define CYVAL__DDFT0_SEL_ACT_POWER_EN 0x00000002u
#define CYVAL__DDFT0_SEL_ACT_POWER_UP 0x00000003u
#define CYVAL__DDFT0_SEL_ACT_POWER_GOOD 0x00000004u
#define CYVAL__DDFT0_SEL_ACT_REF_EN 0x00000005u
#define CYVAL__DDFT0_SEL_ACT_COMP_EN 0x00000006u
#define CYVAL__DDFT0_SEL_DPSLP_REF_EN 0x00000007u
#define CYVAL__DDFT0_SEL_DPSLP_REG_EN 0x00000008u
#define CYVAL__DDFT0_SEL_DPSLP_COMP_EN 0x00000009u
#define CYVAL__DDFT0_SEL_OVER_TEMP_EN 0x0000000au
#define CYVAL__DDFT0_SEL_SLEEPHOLDREQ_N 0x0000000bu
#define CYVAL__DDFT0_SEL_ADFT_BUF_EN 0x0000000cu
#define CYVAL__DDFT0_SEL_ATPG_OBSERVE 0x0000000du
#define CYVAL__DDFT0_SEL_GND 0x0000000eu
#define CYVAL__DDFT0_SEL_PWR 0x0000000fu
#define CYFLD__DDFT1_SEL__OFFSET 0x00000004u
#define CYFLD__DDFT1_SEL__SIZE 0x00000004u
#define CYVAL__DDFT1_SEL_WAKEUP 0x00000000u
#define CYVAL__DDFT1_SEL_AWAKE 0x00000001u
#define CYVAL__DDFT1_SEL_ACT_POWER_EN 0x00000002u
#define CYVAL__DDFT1_SEL_ACT_POWER_UP 0x00000003u
#define CYVAL__DDFT1_SEL_ACT_POWER_GOOD 0x00000004u
#define CYVAL__DDFT1_SEL_ACT_REF_VALID 0x00000005u
#define CYVAL__DDFT1_SEL_ACT_REG_VALID 0x00000006u
#define CYVAL__DDFT1_SEL_ACT_COMP_OUT 0x00000007u
#define CYVAL__DDFT1_SEL_ACT_TEMP_HIGH 0x00000008u
#define CYVAL__DDFT1_SEL_DPSLP_COMP_OUT 0x00000009u
#define CYVAL__DDFT1_SEL_DPSLP_POWER_UP 0x0000000au
#define CYVAL__DDFT1_SEL_AWAKE_DELAYED 0x0000000bu
#define CYVAL__DDFT1_SEL_LPM_READY 0x0000000cu
#define CYVAL__DDFT1_SEL_SLEEPHOLDACK_N 0x0000000du
#define CYVAL__DDFT1_SEL_GND 0x0000000eu
#define CYVAL__DDFT1_SEL_PWR 0x0000000fu
#define CYREG_TST_MODE 0x40030014u
#define CYFLD__SWD_CONNECTED__OFFSET 0x00000002u
#define CYFLD__SWD_CONNECTED__SIZE 0x00000001u
#define CYFLD__BLOCK_ALT_XRES__OFFSET 0x0000001cu
#define CYFLD__BLOCK_ALT_XRES__SIZE 0x00000001u
#define CYFLD__TEST_KEY_DFT_EN__OFFSET 0x0000001eu
#define CYFLD__TEST_KEY_DFT_EN__SIZE 0x00000001u
#define CYFLD__TEST_MODE__OFFSET 0x0000001fu
#define CYFLD__TEST_MODE__SIZE 0x00000001u
#define CYREG_TST_DDFT_CTRL 0x40030018u
#define CYFLD__DFT_SEL0__OFFSET 0x00000000u
#define CYFLD__DFT_SEL0__SIZE 0x00000004u
#define CYVAL__DFT_SEL0_SRC0 0x00000000u
#define CYVAL__DFT_SEL0_SRC1 0x00000001u
#define CYVAL__DFT_SEL0_SRC2 0x00000002u
#define CYVAL__DFT_SEL0_SRC3 0x00000003u
#define CYVAL__DFT_SEL0_SRC4 0x00000004u
#define CYVAL__DFT_SEL0_SRC5 0x00000005u
#define CYVAL__DFT_SEL0_SRC6 0x00000006u
#define CYVAL__DFT_SEL0_SRC7 0x00000007u
#define CYVAL__DFT_SEL0_CLK0 0x00000008u
#define CYVAL__DFT_SEL0_CLK1 0x00000009u
#define CYVAL__DFT_SEL0_PWR0 0x0000000au
#define CYVAL__DFT_SEL0_PWR1 0x0000000bu
#define CYVAL__DFT_SEL0_RES0 0x0000000cu
#define CYVAL__DFT_SEL0_RES1 0x0000000du
#define CYVAL__DFT_SEL0_ADFT_COMP 0x0000000eu
#define CYVAL__DFT_SEL0_VSS 0x0000000fu
#define CYFLD__DFT_SEL1__OFFSET 0x00000008u
#define CYFLD__DFT_SEL1__SIZE 0x00000004u
#define CYVAL__DFT_SEL1_SRC0 0x00000000u
#define CYVAL__DFT_SEL1_SRC1 0x00000001u
#define CYVAL__DFT_SEL1_SRC2 0x00000002u
#define CYVAL__DFT_SEL1_SRC3 0x00000003u
#define CYVAL__DFT_SEL1_SRC4 0x00000004u
#define CYVAL__DFT_SEL1_SRC5 0x00000005u
#define CYVAL__DFT_SEL1_SRC6 0x00000006u
#define CYVAL__DFT_SEL1_SRC7 0x00000007u
#define CYVAL__DFT_SEL1_CLK0 0x00000008u
#define CYVAL__DFT_SEL1_CLK1 0x00000009u
#define CYVAL__DFT_SEL1_PWR0 0x0000000au
#define CYVAL__DFT_SEL1_PWR1 0x0000000bu
#define CYVAL__DFT_SEL1_RES0 0x0000000cu
#define CYVAL__DFT_SEL1_RES1 0x0000000du
#define CYVAL__DFT_SEL1_ADFT_COMP 0x0000000eu
#define CYVAL__DFT_SEL1_VSS 0x0000000fu
#define CYFLD__ENABLE__OFFSET 0x0000001fu
#define CYFLD__ENABLE__SIZE 0x00000001u
#define CYREG_TST_TRIM_CNTR1 0x4003001cu
#define CYFLD__COUNTER__OFFSET 0x00000000u
#define CYFLD__COUNTER__SIZE 0x00000010u
#define CYFLD__COUNTER_DONE__OFFSET 0x0000001fu
#define CYFLD__COUNTER_DONE__SIZE 0x00000001u
#define CYREG_TST_TRIM_CNTR2 0x40030020u
#define CYREG_TST_ADFT_CTRL 0x40030024u
#define CYFLD__BUF_AUTO_ZERO__OFFSET 0x00000000u
#define CYFLD__BUF_AUTO_ZERO__SIZE 0x00000001u
#define CYFLD__BUF_MODE__OFFSET 0x00000008u
#define CYFLD__BUF_MODE__SIZE 0x00000002u
#define CYFLD__BUF_COMP_OUT__OFFSET 0x00000010u
#define CYFLD__BUF_COMP_OUT__SIZE 0x00000001u
#define CYFLD__BUF_EN__OFFSET 0x0000001fu
#define CYFLD__BUF_EN__SIZE 0x00000001u
#define CYREG_CLK_SELECT 0x40030028u
#define CYFLD__HFCLK_SEL__OFFSET 0x00000000u
#define CYFLD__HFCLK_SEL__SIZE 0x00000002u
#define CYVAL__HFCLK_SEL_IMO 0x00000000u
#define CYVAL__HFCLK_SEL_EXTCLK 0x00000001u
#define CYVAL__HFCLK_SEL_ECO 0x00000002u
#define CYFLD__HFCLK_DIV__OFFSET 0x00000002u
#define CYFLD__HFCLK_DIV__SIZE 0x00000002u
#define CYVAL__HFCLK_DIV_NO_DIV 0x00000000u
#define CYVAL__HFCLK_DIV_DIV_BY_2 0x00000001u
#define CYVAL__HFCLK_DIV_DIV_BY_4 0x00000002u
#define CYVAL__HFCLK_DIV_DIV_BY_8 0x00000003u
#define CYFLD__PUMP_SEL__OFFSET 0x00000004u
#define CYFLD__PUMP_SEL__SIZE 0x00000002u
#define CYVAL__PUMP_SEL_GND 0x00000000u
#define CYVAL__PUMP_SEL_IMO 0x00000001u
#define CYVAL__PUMP_SEL_HFCLK 0x00000002u
#define CYFLD__SYSCLK_DIV__OFFSET 0x00000006u
#define CYFLD__SYSCLK_DIV__SIZE 0x00000002u
#define CYVAL__SYSCLK_DIV_NO_DIV 0x00000000u
#define CYVAL__SYSCLK_DIV_DIV_BY_2 0x00000001u
#define CYVAL__SYSCLK_DIV_DIV_BY_4 0x00000002u
#define CYVAL__SYSCLK_DIV_DIV_BY_8 0x00000003u
#define CYREG_CLK_ILO_CONFIG 0x4003002cu
#define CYREG_CLK_IMO_CONFIG 0x40030030u
#define CYREG_CLK_DFT_SELECT 0x40030034u
#define CYFLD__DFT_DIV0__OFFSET 0x00000004u
#define CYFLD__DFT_DIV0__SIZE 0x00000002u
#define CYVAL__DFT_DIV0_NO_DIV 0x00000000u
#define CYVAL__DFT_DIV0_DIV_BY_2 0x00000001u
#define CYVAL__DFT_DIV0_DIV_BY_4 0x00000002u
#define CYVAL__DFT_DIV0_DIV_BY_8 0x00000003u
#define CYFLD__DFT_EDGE0__OFFSET 0x00000006u
#define CYFLD__DFT_EDGE0__SIZE 0x00000001u
#define CYVAL__DFT_EDGE0_POSEDGE 0x00000000u
#define CYVAL__DFT_EDGE0_NEGEDGE 0x00000001u
#define CYFLD__DFT_DIV1__OFFSET 0x0000000cu
#define CYFLD__DFT_DIV1__SIZE 0x00000002u
#define CYVAL__DFT_DIV1_NO_DIV 0x00000000u
#define CYVAL__DFT_DIV1_DIV_BY_2 0x00000001u
#define CYVAL__DFT_DIV1_DIV_BY_4 0x00000002u
#define CYVAL__DFT_DIV1_DIV_BY_8 0x00000003u
#define CYFLD__DFT_EDGE1__OFFSET 0x0000000eu
#define CYFLD__DFT_EDGE1__SIZE 0x00000001u
#define CYVAL__DFT_EDGE1_POSEDGE 0x00000000u
#define CYVAL__DFT_EDGE1_NEGEDGE 0x00000001u
#define CYREG_WDT_DISABLE_KEY 0x40030038u
#define CYFLD__KEY__OFFSET 0x00000000u
#define CYFLD__KEY__SIZE 0x00000020u
#define CYREG_WDT_COUNTER 0x4003003cu
#define CYREG_WDT_MATCH 0x40030040u
#define CYFLD__MATCH__OFFSET 0x00000000u
#define CYFLD__MATCH__SIZE 0x00000010u
#define CYFLD__IGNORE_BITS__OFFSET 0x00000010u
#define CYFLD__IGNORE_BITS__SIZE 0x00000004u
#define CYREG_SRSS_INTR 0x40030044u
#define CYFLD__WDT_MATCH__OFFSET 0x00000000u
#define CYFLD__WDT_MATCH__SIZE 0x00000001u
#define CYFLD__TEMP_HIGH__OFFSET 0x00000001u
#define CYFLD__TEMP_HIGH__SIZE 0x00000001u
#define CYREG_SRSS_INTR_SET 0x40030048u
#define CYREG_SRSS_INTR_MASK 0x4003004cu
#define CYREG_RES_CAUSE 0x40030054u
#define CYFLD__RESET_WDT__OFFSET 0x00000000u
#define CYFLD__RESET_WDT__SIZE 0x00000001u
#define CYFLD__RESET_PROT_FAULT__OFFSET 0x00000003u
#define CYFLD__RESET_PROT_FAULT__SIZE 0x00000001u
#define CYFLD__RESET_SOFT__OFFSET 0x00000004u
#define CYFLD__RESET_SOFT__SIZE 0x00000001u
#define CYREG_PWR_BG_TRIM1 0x40030f00u
#define CYFLD__REF_VTRIM__OFFSET 0x00000000u
#define CYFLD__REF_VTRIM__SIZE 0x00000006u
#define CYREG_PWR_BG_TRIM2 0x40030f04u
#define CYFLD__REF_ITRIM__OFFSET 0x00000000u
#define CYFLD__REF_ITRIM__SIZE 0x00000006u
#define CYREG_CLK_IMO_SELECT 0x40030f08u
#define CYFLD__FREQ__OFFSET 0x00000000u
#define CYFLD__FREQ__SIZE 0x00000003u
#define CYVAL__FREQ_24_MHZ 0x00000000u
#define CYVAL__FREQ_28_MHZ 0x00000001u
#define CYVAL__FREQ_32_MHZ 0x00000002u
#define CYVAL__FREQ_36_MHZ 0x00000003u
#define CYVAL__FREQ_40_MHZ 0x00000004u
#define CYVAL__FREQ_44_MHZ 0x00000005u
#define CYVAL__FREQ_48_MHZ 0x00000006u
#define CYREG_CLK_IMO_TRIM1 0x40030f0cu
#define CYFLD__OFFSET__OFFSET 0x00000000u
#define CYFLD__OFFSET__SIZE 0x00000008u
#define CYREG_CLK_IMO_TRIM2 0x40030f10u
#define CYFLD__FSOFFSET__OFFSET 0x00000000u
#define CYFLD__FSOFFSET__SIZE 0x00000003u
#define CYREG_PWR_PWRSYS_TRIM1 0x40030f14u
#define CYFLD__DPSLP_REF_TRIM__OFFSET 0x00000000u
#define CYFLD__DPSLP_REF_TRIM__SIZE 0x00000004u
#define CYFLD__SPARE_TRIM__OFFSET 0x00000004u
#define CYFLD__SPARE_TRIM__SIZE 0x00000004u
#define CYREG_CLK_IMO_TRIM3 0x40030f18u
#define CYFLD__STEPSIZE__OFFSET 0x00000000u
#define CYFLD__STEPSIZE__SIZE 0x00000005u
#define CYFLD__TCTRIM__OFFSET 0x00000005u
#define CYFLD__TCTRIM__SIZE 0x00000002u
#define CYDEV_GPIO_BASE 0x40040000u
#define CYDEV_GPIO_SIZE 0x00004000u
#define CYDEV_GPIO_PRT0_BASE 0x40040000u
#define CYDEV_GPIO_PRT0_SIZE 0x00000100u
#define CYREG_GPIO_PRT0_DR 0x40040000u
#define CYFLD_GPIO_PRT_DATA0__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_DATA0__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA1__OFFSET 0x00000001u
#define CYFLD_GPIO_PRT_DATA1__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA2__OFFSET 0x00000002u
#define CYFLD_GPIO_PRT_DATA2__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA3__OFFSET 0x00000003u
#define CYFLD_GPIO_PRT_DATA3__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA4__OFFSET 0x00000004u
#define CYFLD_GPIO_PRT_DATA4__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA5__OFFSET 0x00000005u
#define CYFLD_GPIO_PRT_DATA5__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA6__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_DATA6__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_DATA7__OFFSET 0x00000007u
#define CYFLD_GPIO_PRT_DATA7__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_PS 0x40040004u
#define CYFLD_GPIO_PRT_FLT_DATA__OFFSET 0x00000008u
#define CYFLD_GPIO_PRT_FLT_DATA__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_PC 0x40040008u
#define CYFLD_GPIO_PRT_DM0__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_DM0__SIZE 0x00000003u
#define CYVAL_GPIO_PRT_DM0_OFF 0x00000000u
#define CYVAL_GPIO_PRT_DM0_INPUT 0x00000001u
#define CYVAL_GPIO_PRT_DM0_0_PU 0x00000002u
#define CYVAL_GPIO_PRT_DM0_PD_1 0x00000003u
#define CYVAL_GPIO_PRT_DM0_0_Z 0x00000004u
#define CYVAL_GPIO_PRT_DM0_Z_1 0x00000005u
#define CYVAL_GPIO_PRT_DM0_0_1 0x00000006u
#define CYVAL_GPIO_PRT_DM0_PD_PU 0x00000007u
#define CYFLD_GPIO_PRT_DM1__OFFSET 0x00000003u
#define CYFLD_GPIO_PRT_DM1__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM2__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_DM2__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM3__OFFSET 0x00000009u
#define CYFLD_GPIO_PRT_DM3__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM4__OFFSET 0x0000000cu
#define CYFLD_GPIO_PRT_DM4__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM5__OFFSET 0x0000000fu
#define CYFLD_GPIO_PRT_DM5__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM6__OFFSET 0x00000012u
#define CYFLD_GPIO_PRT_DM6__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_DM7__OFFSET 0x00000015u
#define CYFLD_GPIO_PRT_DM7__SIZE 0x00000003u
#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__OFFSET 0x00000018u
#define CYFLD_GPIO_PRT_PORT_VTRIP_SEL__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PORT_SLOW__OFFSET 0x00000019u
#define CYFLD_GPIO_PRT_PORT_SLOW__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__OFFSET 0x0000001eu
#define CYFLD_GPIO_PRT_PORT_IB_MODE_SEL__SIZE 0x00000002u
#define CYREG_GPIO_PRT0_INTR_CFG 0x4004000cu
#define CYFLD_GPIO_PRT_EDGE0_SEL__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_EDGE0_SEL__SIZE 0x00000002u
#define CYVAL_GPIO_PRT_EDGE0_SEL_DISABLE 0x00000000u
#define CYVAL_GPIO_PRT_EDGE0_SEL_RISING 0x00000001u
#define CYVAL_GPIO_PRT_EDGE0_SEL_FALLING 0x00000002u
#define CYVAL_GPIO_PRT_EDGE0_SEL_BOTH 0x00000003u
#define CYFLD_GPIO_PRT_EDGE1_SEL__OFFSET 0x00000002u
#define CYFLD_GPIO_PRT_EDGE1_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE2_SEL__OFFSET 0x00000004u
#define CYFLD_GPIO_PRT_EDGE2_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE3_SEL__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_EDGE3_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE4_SEL__OFFSET 0x00000008u
#define CYFLD_GPIO_PRT_EDGE4_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE5_SEL__OFFSET 0x0000000au
#define CYFLD_GPIO_PRT_EDGE5_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE6_SEL__OFFSET 0x0000000cu
#define CYFLD_GPIO_PRT_EDGE6_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_EDGE7_SEL__OFFSET 0x0000000eu
#define CYFLD_GPIO_PRT_EDGE7_SEL__SIZE 0x00000002u
#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__OFFSET 0x00000010u
#define CYFLD_GPIO_PRT_FLT_EDGE_SEL__SIZE 0x00000002u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_DISABLE 0x00000000u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_RISING 0x00000001u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_FALLING 0x00000002u
#define CYVAL_GPIO_PRT_FLT_EDGE_SEL_BOTH 0x00000003u
#define CYFLD_GPIO_PRT_FLT_SEL__OFFSET 0x00000012u
#define CYFLD_GPIO_PRT_FLT_SEL__SIZE 0x00000003u
#define CYREG_GPIO_PRT0_INTR 0x40040010u
#define CYFLD_GPIO_PRT_PS_DATA0__OFFSET 0x00000010u
#define CYFLD_GPIO_PRT_PS_DATA0__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA1__OFFSET 0x00000011u
#define CYFLD_GPIO_PRT_PS_DATA1__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA2__OFFSET 0x00000012u
#define CYFLD_GPIO_PRT_PS_DATA2__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA3__OFFSET 0x00000013u
#define CYFLD_GPIO_PRT_PS_DATA3__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA4__OFFSET 0x00000014u
#define CYFLD_GPIO_PRT_PS_DATA4__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA5__OFFSET 0x00000015u
#define CYFLD_GPIO_PRT_PS_DATA5__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA6__OFFSET 0x00000016u
#define CYFLD_GPIO_PRT_PS_DATA6__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_DATA7__OFFSET 0x00000017u
#define CYFLD_GPIO_PRT_PS_DATA7__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_PS_FLT_DATA__OFFSET 0x00000018u
#define CYFLD_GPIO_PRT_PS_FLT_DATA__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_PC2 0x40040018u
#define CYFLD_GPIO_PRT_INP_DIS0__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_INP_DIS0__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS1__OFFSET 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS1__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS2__OFFSET 0x00000002u
#define CYFLD_GPIO_PRT_INP_DIS2__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS3__OFFSET 0x00000003u
#define CYFLD_GPIO_PRT_INP_DIS3__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS4__OFFSET 0x00000004u
#define CYFLD_GPIO_PRT_INP_DIS4__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS5__OFFSET 0x00000005u
#define CYFLD_GPIO_PRT_INP_DIS5__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS6__OFFSET 0x00000006u
#define CYFLD_GPIO_PRT_INP_DIS6__SIZE 0x00000001u
#define CYFLD_GPIO_PRT_INP_DIS7__OFFSET 0x00000007u
#define CYFLD_GPIO_PRT_INP_DIS7__SIZE 0x00000001u
#define CYREG_GPIO_PRT0_DR_SET 0x40040040u
#define CYFLD_GPIO_PRT_DATA__OFFSET 0x00000000u
#define CYFLD_GPIO_PRT_DATA__SIZE 0x00000008u
#define CYREG_GPIO_PRT0_DR_CLR 0x40040044u
#define CYREG_GPIO_PRT0_DR_INV 0x40040048u
#define CYDEV_GPIO_PRT1_BASE 0x40040100u
#define CYDEV_GPIO_PRT1_SIZE 0x00000100u
#define CYREG_GPIO_PRT1_DR 0x40040100u
#define CYREG_GPIO_PRT1_PS 0x40040104u
#define CYREG_GPIO_PRT1_PC 0x40040108u
#define CYREG_GPIO_PRT1_INTR_CFG 0x4004010cu
#define CYREG_GPIO_PRT1_INTR 0x40040110u
#define CYREG_GPIO_PRT1_PC2 0x40040118u
#define CYREG_GPIO_PRT1_DR_SET 0x40040140u
#define CYREG_GPIO_PRT1_DR_CLR 0x40040144u
#define CYREG_GPIO_PRT1_DR_INV 0x40040148u
#define CYDEV_GPIO_PRT2_BASE 0x40040200u
#define CYDEV_GPIO_PRT2_SIZE 0x00000100u
#define CYREG_GPIO_PRT2_DR 0x40040200u
#define CYREG_GPIO_PRT2_PS 0x40040204u
#define CYREG_GPIO_PRT2_PC 0x40040208u
#define CYREG_GPIO_PRT2_INTR_CFG 0x4004020cu
#define CYREG_GPIO_PRT2_INTR 0x40040210u
#define CYREG_GPIO_PRT2_PC2 0x40040218u
#define CYREG_GPIO_PRT2_DR_SET 0x40040240u
#define CYREG_GPIO_PRT2_DR_CLR 0x40040244u
#define CYREG_GPIO_PRT2_DR_INV 0x40040248u
#define CYDEV_GPIO_PRT3_BASE 0x40040300u
#define CYDEV_GPIO_PRT3_SIZE 0x00000100u
#define CYREG_GPIO_PRT3_DR 0x40040300u
#define CYREG_GPIO_PRT3_PS 0x40040304u
#define CYREG_GPIO_PRT3_PC 0x40040308u
#define CYREG_GPIO_PRT3_INTR_CFG 0x4004030cu
#define CYREG_GPIO_PRT3_INTR 0x40040310u
#define CYREG_GPIO_PRT3_PC2 0x40040318u
#define CYREG_GPIO_PRT3_DR_SET 0x40040340u
#define CYREG_GPIO_PRT3_DR_CLR 0x40040344u
#define CYREG_GPIO_PRT3_DR_INV 0x40040348u
#define CYDEV_GPIO_PRT4_BASE 0x40040400u
#define CYDEV_GPIO_PRT4_SIZE 0x00000100u
#define CYREG_GPIO_PRT4_DR 0x40040400u
#define CYREG_GPIO_PRT4_PS 0x40040404u
#define CYREG_GPIO_PRT4_PC 0x40040408u
#define CYREG_GPIO_PRT4_INTR_CFG 0x4004040cu
#define CYREG_GPIO_PRT4_INTR 0x40040410u
#define CYREG_GPIO_PRT4_PC2 0x40040418u
#define CYREG_GPIO_PRT4_DR_SET 0x40040440u
#define CYREG_GPIO_PRT4_DR_CLR 0x40040444u
#define CYREG_GPIO_PRT4_DR_INV 0x40040448u
#define CYDEV_GPIO_PRT5_BASE 0x40040500u
#define CYDEV_GPIO_PRT5_SIZE 0x00000100u
#define CYREG_GPIO_PRT5_DR 0x40040500u
#define CYREG_GPIO_PRT5_PS 0x40040504u
#define CYREG_GPIO_PRT5_PC 0x40040508u
#define CYREG_GPIO_PRT5_INTR_CFG 0x4004050cu
#define CYREG_GPIO_PRT5_INTR 0x40040510u
#define CYREG_GPIO_PRT5_PC2 0x40040518u
#define CYREG_GPIO_PRT5_DR_SET 0x40040540u
#define CYREG_GPIO_PRT5_DR_CLR 0x40040544u
#define CYREG_GPIO_PRT5_DR_INV 0x40040548u
#define CYDEV_GPIO_PRT6_BASE 0x40040600u
#define CYDEV_GPIO_PRT6_SIZE 0x00000100u
#define CYREG_GPIO_PRT6_DR 0x40040600u
#define CYREG_GPIO_PRT6_PS 0x40040604u
#define CYREG_GPIO_PRT6_PC 0x40040608u
#define CYREG_GPIO_PRT6_INTR_CFG 0x4004060cu
#define CYREG_GPIO_PRT6_INTR 0x40040610u
#define CYREG_GPIO_PRT6_PC2 0x40040618u
#define CYREG_GPIO_PRT6_DR_SET 0x40040640u
#define CYREG_GPIO_PRT6_DR_CLR 0x40040644u
#define CYREG_GPIO_PRT6_DR_INV 0x40040648u
#define CYDEV_GPIO_PRT7_BASE 0x40040700u
#define CYDEV_GPIO_PRT7_SIZE 0x00000100u
#define CYREG_GPIO_PRT7_DR 0x40040700u
#define CYREG_GPIO_PRT7_PS 0x40040704u
#define CYREG_GPIO_PRT7_PC 0x40040708u
#define CYREG_GPIO_PRT7_INTR_CFG 0x4004070cu
#define CYREG_GPIO_PRT7_INTR 0x40040710u
#define CYREG_GPIO_PRT7_PC2 0x40040718u
#define CYREG_GPIO_PRT7_DR_SET 0x40040740u
#define CYREG_GPIO_PRT7_DR_CLR 0x40040744u
#define CYREG_GPIO_PRT7_DR_INV 0x40040748u
#define CYREG_GPIO_INTR_CAUSE 0x40041000u
#define CYFLD_GPIO_PORT_INT__OFFSET 0x00000000u
#define CYFLD_GPIO_PORT_INT__SIZE 0x00000008u
#define CYDEV_PRGIO_BASE 0x40050000u
#define CYDEV_PRGIO_SIZE 0x00001000u
#define CYDEV_PRGIO_PRT0_BASE 0x40050000u
#define CYDEV_PRGIO_PRT0_SIZE 0x00000100u
#define CYREG_PRGIO_PRT0_CTL 0x40050000u
#define CYFLD_PRGIO_PRT_BYPASS__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_BYPASS__SIZE 0x00000008u
#define CYFLD_PRGIO_PRT_CLOCK_SRC__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_CLOCK_SRC__SIZE 0x00000005u
#define CYFLD_PRGIO_PRT_HLD_OVR__OFFSET 0x00000018u
#define CYFLD_PRGIO_PRT_HLD_OVR__SIZE 0x00000001u
#define CYFLD_PRGIO_PRT_PIPELINE_EN__OFFSET 0x00000019u
#define CYFLD_PRGIO_PRT_PIPELINE_EN__SIZE 0x00000001u
#define CYFLD_PRGIO_PRT_ENABLED__OFFSET 0x0000001fu
#define CYFLD_PRGIO_PRT_ENABLED__SIZE 0x00000001u
#define CYREG_PRGIO_PRT0_SYNC_CTL 0x40050010u
#define CYFLD_PRGIO_PRT_IO_SYNC_EN__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_IO_SYNC_EN__SIZE 0x00000008u
#define CYFLD_PRGIO_PRT_CHIP_SYNC_EN__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_CHIP_SYNC_EN__SIZE 0x00000008u
#define CYREG_PRGIO_PRT0_LUT_SEL0 0x40050020u
#define CYFLD_PRGIO_PRT_LUT_TR0_SEL__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_LUT_TR0_SEL__SIZE 0x00000004u
#define CYFLD_PRGIO_PRT_LUT_TR1_SEL__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_LUT_TR1_SEL__SIZE 0x00000004u
#define CYFLD_PRGIO_PRT_LUT_TR2_SEL__OFFSET 0x00000010u
#define CYFLD_PRGIO_PRT_LUT_TR2_SEL__SIZE 0x00000004u
#define CYREG_PRGIO_PRT0_LUT_SEL1 0x40050024u
#define CYREG_PRGIO_PRT0_LUT_SEL2 0x40050028u
#define CYREG_PRGIO_PRT0_LUT_SEL3 0x4005002cu
#define CYREG_PRGIO_PRT0_LUT_SEL4 0x40050030u
#define CYREG_PRGIO_PRT0_LUT_SEL5 0x40050034u
#define CYREG_PRGIO_PRT0_LUT_SEL6 0x40050038u
#define CYREG_PRGIO_PRT0_LUT_SEL7 0x4005003cu
#define CYREG_PRGIO_PRT0_LUT_CTL0 0x40050040u
#define CYFLD_PRGIO_PRT_LUT__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_LUT__SIZE 0x00000008u
#define CYFLD_PRGIO_PRT_LUT_OPC__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_LUT_OPC__SIZE 0x00000002u
#define CYREG_PRGIO_PRT0_LUT_CTL1 0x40050044u
#define CYREG_PRGIO_PRT0_LUT_CTL2 0x40050048u
#define CYREG_PRGIO_PRT0_LUT_CTL3 0x4005004cu
#define CYREG_PRGIO_PRT0_LUT_CTL4 0x40050050u
#define CYREG_PRGIO_PRT0_LUT_CTL5 0x40050054u
#define CYREG_PRGIO_PRT0_LUT_CTL6 0x40050058u
#define CYREG_PRGIO_PRT0_LUT_CTL7 0x4005005cu
#define CYREG_PRGIO_PRT0_DU_SEL 0x400500c0u
#define CYFLD_PRGIO_PRT_DU_TR0_SEL__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_DU_TR0_SEL__SIZE 0x00000004u
#define CYFLD_PRGIO_PRT_DU_TR1_SEL__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_DU_TR1_SEL__SIZE 0x00000004u
#define CYFLD_PRGIO_PRT_DU_TR2_SEL__OFFSET 0x00000010u
#define CYFLD_PRGIO_PRT_DU_TR2_SEL__SIZE 0x00000004u
#define CYFLD_PRGIO_PRT_DU_DATA0_SEL__OFFSET 0x00000018u
#define CYFLD_PRGIO_PRT_DU_DATA0_SEL__SIZE 0x00000002u
#define CYFLD_PRGIO_PRT_DU_DATA1_SEL__OFFSET 0x0000001cu
#define CYFLD_PRGIO_PRT_DU_DATA1_SEL__SIZE 0x00000002u
#define CYREG_PRGIO_PRT0_DU_CTL 0x400500c4u
#define CYFLD_PRGIO_PRT_DU_SIZE__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_DU_SIZE__SIZE 0x00000003u
#define CYFLD_PRGIO_PRT_DU_OPC__OFFSET 0x00000008u
#define CYFLD_PRGIO_PRT_DU_OPC__SIZE 0x00000004u
#define CYREG_PRGIO_PRT0_DATA 0x400500f0u
#define CYFLD_PRGIO_PRT_DATA__OFFSET 0x00000000u
#define CYFLD_PRGIO_PRT_DATA__SIZE 0x00000008u
#define CYDEV_PRGIO_PRT1_BASE 0x40050100u
#define CYDEV_PRGIO_PRT1_SIZE 0x00000100u
#define CYREG_PRGIO_PRT1_CTL 0x40050100u
#define CYREG_PRGIO_PRT1_SYNC_CTL 0x40050110u
#define CYREG_PRGIO_PRT1_LUT_SEL0 0x40050120u
#define CYREG_PRGIO_PRT1_LUT_SEL1 0x40050124u
#define CYREG_PRGIO_PRT1_LUT_SEL2 0x40050128u
#define CYREG_PRGIO_PRT1_LUT_SEL3 0x4005012cu
#define CYREG_PRGIO_PRT1_LUT_SEL4 0x40050130u
#define CYREG_PRGIO_PRT1_LUT_SEL5 0x40050134u
#define CYREG_PRGIO_PRT1_LUT_SEL6 0x40050138u
#define CYREG_PRGIO_PRT1_LUT_SEL7 0x4005013cu
#define CYREG_PRGIO_PRT1_LUT_CTL0 0x40050140u
#define CYREG_PRGIO_PRT1_LUT_CTL1 0x40050144u
#define CYREG_PRGIO_PRT1_LUT_CTL2 0x40050148u
#define CYREG_PRGIO_PRT1_LUT_CTL3 0x4005014cu
#define CYREG_PRGIO_PRT1_LUT_CTL4 0x40050150u
#define CYREG_PRGIO_PRT1_LUT_CTL5 0x40050154u
#define CYREG_PRGIO_PRT1_LUT_CTL6 0x40050158u
#define CYREG_PRGIO_PRT1_LUT_CTL7 0x4005015cu
#define CYREG_PRGIO_PRT1_DU_SEL 0x400501c0u
#define CYREG_PRGIO_PRT1_DU_CTL 0x400501c4u
#define CYREG_PRGIO_PRT1_DATA 0x400501f0u
#define CYDEV_PRGIO_PRT2_BASE 0x40050200u
#define CYDEV_PRGIO_PRT2_SIZE 0x00000100u
#define CYREG_PRGIO_PRT2_CTL 0x40050200u
#define CYREG_PRGIO_PRT2_SYNC_CTL 0x40050210u
#define CYREG_PRGIO_PRT2_LUT_SEL0 0x40050220u
#define CYREG_PRGIO_PRT2_LUT_SEL1 0x40050224u
#define CYREG_PRGIO_PRT2_LUT_SEL2 0x40050228u
#define CYREG_PRGIO_PRT2_LUT_SEL3 0x4005022cu
#define CYREG_PRGIO_PRT2_LUT_SEL4 0x40050230u
#define CYREG_PRGIO_PRT2_LUT_SEL5 0x40050234u
#define CYREG_PRGIO_PRT2_LUT_SEL6 0x40050238u
#define CYREG_PRGIO_PRT2_LUT_SEL7 0x4005023cu
#define CYREG_PRGIO_PRT2_LUT_CTL0 0x40050240u
#define CYREG_PRGIO_PRT2_LUT_CTL1 0x40050244u
#define CYREG_PRGIO_PRT2_LUT_CTL2 0x40050248u
#define CYREG_PRGIO_PRT2_LUT_CTL3 0x4005024cu
#define CYREG_PRGIO_PRT2_LUT_CTL4 0x40050250u
#define CYREG_PRGIO_PRT2_LUT_CTL5 0x40050254u
#define CYREG_PRGIO_PRT2_LUT_CTL6 0x40050258u
#define CYREG_PRGIO_PRT2_LUT_CTL7 0x4005025cu
#define CYREG_PRGIO_PRT2_DU_SEL 0x400502c0u
#define CYREG_PRGIO_PRT2_DU_CTL 0x400502c4u
#define CYREG_PRGIO_PRT2_DATA 0x400502f0u
#define CYDEV_CPUSS_BASE 0x40100000u
#define CYDEV_CPUSS_SIZE 0x00001000u
#define CYREG_CPUSS_SYSREQ 0x40100004u
#define CYFLD_CPUSS_SYSCALL_COMMAND__OFFSET 0x00000000u
#define CYFLD_CPUSS_SYSCALL_COMMAND__SIZE 0x00000010u
#define CYFLD_CPUSS_DIS_RESET_VECT_REL__OFFSET 0x0000001bu
#define CYFLD_CPUSS_DIS_RESET_VECT_REL__SIZE 0x00000001u
#define CYFLD_CPUSS_PRIVILEGED__OFFSET 0x0000001cu
#define CYFLD_CPUSS_PRIVILEGED__SIZE 0x00000001u
#define CYFLD_CPUSS_ROM_ACCESS_EN__OFFSET 0x0000001du
#define CYFLD_CPUSS_ROM_ACCESS_EN__SIZE 0x00000001u
#define CYFLD_CPUSS_HMASTER_0__OFFSET 0x0000001eu
#define CYFLD_CPUSS_HMASTER_0__SIZE 0x00000001u
#define CYFLD_CPUSS_SYSCALL_REQ__OFFSET 0x0000001fu
#define CYFLD_CPUSS_SYSCALL_REQ__SIZE 0x00000001u
#define CYREG_CPUSS_SYSARG 0x40100008u
#define CYFLD_CPUSS_SYSCALL_ARG__OFFSET 0x00000000u
#define CYFLD_CPUSS_SYSCALL_ARG__SIZE 0x00000020u
#define CYREG_CPUSS_PROTECTION 0x4010000cu
#define CYFLD_CPUSS_PROTECTION_MODE__OFFSET 0x00000000u
#define CYFLD_CPUSS_PROTECTION_MODE__SIZE 0x00000004u
#define CYFLD_CPUSS_FLASH_LOCK__OFFSET 0x0000001eu
#define CYFLD_CPUSS_FLASH_LOCK__SIZE 0x00000001u
#define CYFLD_CPUSS_PROTECTION_LOCK__OFFSET 0x0000001fu
#define CYFLD_CPUSS_PROTECTION_LOCK__SIZE 0x00000001u
#define CYREG_CPUSS_PRIV_ROM 0x40100010u
#define CYFLD_CPUSS_BROM_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_BROM_PROT_LIMIT__SIZE 0x00000008u
#define CYREG_CPUSS_PRIV_RAM 0x40100014u
#define CYFLD_CPUSS_RAM_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_RAM_PROT_LIMIT__SIZE 0x00000009u
#define CYREG_CPUSS_PRIV_FLASH 0x40100018u
#define CYFLD_CPUSS_FLASH_PROT_LIMIT__OFFSET 0x00000000u
#define CYFLD_CPUSS_FLASH_PROT_LIMIT__SIZE 0x0000000cu
#define CYREG_CPUSS_WOUNDING 0x4010001cu
#define CYFLD_CPUSS_RAM_WOUND__OFFSET 0x00000010u
#define CYFLD_CPUSS_RAM_WOUND__SIZE 0x00000003u
#define CYFLD_CPUSS_FLASH_WOUND__OFFSET 0x00000014u
#define CYFLD_CPUSS_FLASH_WOUND__SIZE 0x00000003u
#define CYREG_CPUSS_FLASH_CTL 0x40100030u
#define CYFLD_CPUSS_FLASH_WS__OFFSET 0x00000000u
#define CYFLD_CPUSS_FLASH_WS__SIZE 0x00000002u
#define CYFLD_CPUSS_PREF_EN__OFFSET 0x00000004u
#define CYFLD_CPUSS_PREF_EN__SIZE 0x00000001u
#define CYFLD_CPUSS_FLASH_INVALIDATE__OFFSET 0x00000008u
#define CYFLD_CPUSS_FLASH_INVALIDATE__SIZE 0x00000001u
#define CYFLD_CPUSS_ARB__OFFSET 0x00000010u
#define CYFLD_CPUSS_ARB__SIZE 0x00000002u
#define CYREG_CPUSS_ROM_CTL 0x40100034u
#define CYFLD_CPUSS_ROM_WS__OFFSET 0x00000000u
#define CYFLD_CPUSS_ROM_WS__SIZE 0x00000001u
#define CYREG_CPUSS_RAM_CTL 0x40100038u
#define CYREG_CPUSS_DMAC_CTL 0x4010003cu
#define CYREG_CPUSS_SL_CTL0 0x40100100u
#define CYREG_CPUSS_SL_CTL1 0x40100104u
#define CYREG_CPUSS_SL_CTL2 0x40100108u
#define CYDEV_DMAC_BASE 0x40101000u
#define CYDEV_DMAC_SIZE 0x00001000u
#define CYREG_DMAC_CTL 0x40101000u
#define CYFLD_DMAC_ENABLED__OFFSET 0x0000001fu
#define CYFLD_DMAC_ENABLED__SIZE 0x00000001u
#define CYREG_DMAC_STATUS 0x40101010u
#define CYFLD_DMAC_DATA_NR__OFFSET 0x00000000u
#define CYFLD_DMAC_DATA_NR__SIZE 0x00000010u
#define CYFLD_DMAC_CH_ADDR__OFFSET 0x00000010u
#define CYFLD_DMAC_CH_ADDR__SIZE 0x00000003u
#define CYFLD_DMAC_STATE__OFFSET 0x00000018u
#define CYFLD_DMAC_STATE__SIZE 0x00000003u
#define CYFLD_DMAC_PRIO__OFFSET 0x0000001cu
#define CYFLD_DMAC_PRIO__SIZE 0x00000002u
#define CYFLD_DMAC_PING_PONG__OFFSET 0x0000001eu
#define CYFLD_DMAC_PING_PONG__SIZE 0x00000001u
#define CYFLD_DMAC_ACTIVE__OFFSET 0x0000001fu
#define CYFLD_DMAC_ACTIVE__SIZE 0x00000001u
#define CYREG_DMAC_STATUS_SRC_ADDR 0x40101014u
#define CYFLD_DMAC_ADDR__OFFSET 0x00000000u
#define CYFLD_DMAC_ADDR__SIZE 0x00000020u
#define CYREG_DMAC_STATUS_DST_ADDR 0x40101018u
#define CYREG_DMAC_STATUS_CH_ACT 0x4010101cu
#define CYFLD_DMAC_CH__OFFSET 0x00000000u
#define CYFLD_DMAC_CH__SIZE 0x00000008u
#define CYREG_DMAC_CH_CTL0 0x40101080u
#define CYREG_DMAC_CH_CTL1 0x40101084u
#define CYREG_DMAC_CH_CTL2 0x40101088u
#define CYREG_DMAC_CH_CTL3 0x4010108cu
#define CYREG_DMAC_CH_CTL4 0x40101090u
#define CYREG_DMAC_CH_CTL5 0x40101094u
#define CYREG_DMAC_CH_CTL6 0x40101098u
#define CYREG_DMAC_CH_CTL7 0x4010109cu
#define CYREG_DMAC_INTR 0x401017f0u
#define CYREG_DMAC_INTR_SET 0x401017f4u
#define CYREG_DMAC_INTR_MASK 0x401017f8u
#define CYREG_DMAC_INTR_MASKED 0x401017fcu
#define CYDEV_DMAC_DESCR0_BASE 0x40101800u
#define CYDEV_DMAC_DESCR0_SIZE 0x00000020u
#define CYREG_DMAC_DESCR0_PING_SRC 0x40101800u
#define CYFLD_DMAC_DESCR_ADDR__OFFSET 0x00000000u
#define CYFLD_DMAC_DESCR_ADDR__SIZE 0x00000020u
#define CYREG_DMAC_DESCR0_PING_DST 0x40101804u
#define CYREG_DMAC_DESCR0_PING_CTL 0x40101808u
#define CYFLD_DMAC_DESCR_DATA_NR__OFFSET 0x00000000u
#define CYFLD_DMAC_DESCR_DATA_NR__SIZE 0x00000010u
#define CYFLD_DMAC_DESCR_DATA_SIZE__OFFSET 0x00000010u
#define CYFLD_DMAC_DESCR_DATA_SIZE__SIZE 0x00000002u
#define CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__OFFSET 0x00000014u
#define CYFLD_DMAC_DESCR_DST_TRANSFER_SIZE__SIZE 0x00000001u
#define CYFLD_DMAC_DESCR_DST_ADDR_INCR__OFFSET 0x00000015u
#define CYFLD_DMAC_DESCR_DST_ADDR_INCR__SIZE 0x00000001u
#define CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__OFFSET 0x00000016u
#define CYFLD_DMAC_DESCR_SRC_TRANSFER_SIZE__SIZE 0x00000001u
#define CYFLD_DMAC_DESCR_SRC_ADDR_INCR__OFFSET 0x00000017u
#define CYFLD_DMAC_DESCR_SRC_ADDR_INCR__SIZE 0x00000001u
#define CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__OFFSET 0x00000018u
#define CYFLD_DMAC_DESCR_WAIT_FOR_DEACT__SIZE 0x00000002u
#define CYFLD_DMAC_DESCR_INV_DESCR__OFFSET 0x0000001au
#define CYFLD_DMAC_DESCR_INV_DESCR__SIZE 0x00000001u
#define CYFLD_DMAC_DESCR_SET_CAUSE__OFFSET 0x0000001bu
#define CYFLD_DMAC_DESCR_SET_CAUSE__SIZE 0x00000001u
#define CYFLD_DMAC_DESCR_PREEMPTABLE__OFFSET 0x0000001cu
#define CYFLD_DMAC_DESCR_PREEMPTABLE__SIZE 0x00000001u
#define CYFLD_DMAC_DESCR_FLIPPING__OFFSET 0x0000001du
#define CYFLD_DMAC_DESCR_FLIPPING__SIZE 0x00000001u
#define CYFLD_DMAC_DESCR_OPCODE__OFFSET 0x0000001eu
#define CYFLD_DMAC_DESCR_OPCODE__SIZE 0x00000002u
#define CYREG_DMAC_DESCR0_PING_STATUS 0x4010180cu
#define CYFLD_DMAC_DESCR_CURR_DATA_NR__OFFSET 0x00000000u
#define CYFLD_DMAC_DESCR_CURR_DATA_NR__SIZE 0x00000010u
#define CYFLD_DMAC_DESCR_RESPONSE__OFFSET 0x00000010u
#define CYFLD_DMAC_DESCR_RESPONSE__SIZE 0x00000003u
#define CYFLD_DMAC_DESCR_VALID__OFFSET 0x0000001fu
#define CYFLD_DMAC_DESCR_VALID__SIZE 0x00000001u
#define CYREG_DMAC_DESCR0_PONG_SRC 0x40101810u
#define CYREG_DMAC_DESCR0_PONG_DST 0x40101814u
#define CYREG_DMAC_DESCR0_PONG_CTL 0x40101818u
#define CYREG_DMAC_DESCR0_PONG_STATUS 0x4010181cu
#define CYDEV_DMAC_DESCR1_BASE 0x40101820u
#define CYDEV_DMAC_DESCR1_SIZE 0x00000020u
#define CYREG_DMAC_DESCR1_PING_SRC 0x40101820u
#define CYREG_DMAC_DESCR1_PING_DST 0x40101824u
#define CYREG_DMAC_DESCR1_PING_CTL 0x40101828u
#define CYREG_DMAC_DESCR1_PING_STATUS 0x4010182cu
#define CYREG_DMAC_DESCR1_PONG_SRC 0x40101830u
#define CYREG_DMAC_DESCR1_PONG_DST 0x40101834u
#define CYREG_DMAC_DESCR1_PONG_CTL 0x40101838u
#define CYREG_DMAC_DESCR1_PONG_STATUS 0x4010183cu
#define CYDEV_DMAC_DESCR2_BASE 0x40101840u
#define CYDEV_DMAC_DESCR2_SIZE 0x00000020u
#define CYREG_DMAC_DESCR2_PING_SRC 0x40101840u
#define CYREG_DMAC_DESCR2_PING_DST 0x40101844u
#define CYREG_DMAC_DESCR2_PING_CTL 0x40101848u
#define CYREG_DMAC_DESCR2_PING_STATUS 0x4010184cu
#define CYREG_DMAC_DESCR2_PONG_SRC 0x40101850u
#define CYREG_DMAC_DESCR2_PONG_DST 0x40101854u
#define CYREG_DMAC_DESCR2_PONG_CTL 0x40101858u
#define CYREG_DMAC_DESCR2_PONG_STATUS 0x4010185cu
#define CYDEV_DMAC_DESCR3_BASE 0x40101860u
#define CYDEV_DMAC_DESCR3_SIZE 0x00000020u
#define CYREG_DMAC_DESCR3_PING_SRC 0x40101860u
#define CYREG_DMAC_DESCR3_PING_DST 0x40101864u
#define CYREG_DMAC_DESCR3_PING_CTL 0x40101868u
#define CYREG_DMAC_DESCR3_PING_STATUS 0x4010186cu
#define CYREG_DMAC_DESCR3_PONG_SRC 0x40101870u
#define CYREG_DMAC_DESCR3_PONG_DST 0x40101874u
#define CYREG_DMAC_DESCR3_PONG_CTL 0x40101878u
#define CYREG_DMAC_DESCR3_PONG_STATUS 0x4010187cu
#define CYDEV_DMAC_DESCR4_BASE 0x40101880u
#define CYDEV_DMAC_DESCR4_SIZE 0x00000020u
#define CYREG_DMAC_DESCR4_PING_SRC 0x40101880u
#define CYREG_DMAC_DESCR4_PING_DST 0x40101884u
#define CYREG_DMAC_DESCR4_PING_CTL 0x40101888u
#define CYREG_DMAC_DESCR4_PING_STATUS 0x4010188cu
#define CYREG_DMAC_DESCR4_PONG_SRC 0x40101890u
#define CYREG_DMAC_DESCR4_PONG_DST 0x40101894u
#define CYREG_DMAC_DESCR4_PONG_CTL 0x40101898u
#define CYREG_DMAC_DESCR4_PONG_STATUS 0x4010189cu
#define CYDEV_DMAC_DESCR5_BASE 0x401018a0u
#define CYDEV_DMAC_DESCR5_SIZE 0x00000020u
#define CYREG_DMAC_DESCR5_PING_SRC 0x401018a0u
#define CYREG_DMAC_DESCR5_PING_DST 0x401018a4u
#define CYREG_DMAC_DESCR5_PING_CTL 0x401018a8u
#define CYREG_DMAC_DESCR5_PING_STATUS 0x401018acu
#define CYREG_DMAC_DESCR5_PONG_SRC 0x401018b0u
#define CYREG_DMAC_DESCR5_PONG_DST 0x401018b4u
#define CYREG_DMAC_DESCR5_PONG_CTL 0x401018b8u
#define CYREG_DMAC_DESCR5_PONG_STATUS 0x401018bcu
#define CYDEV_DMAC_DESCR6_BASE 0x401018c0u
#define CYDEV_DMAC_DESCR6_SIZE 0x00000020u
#define CYREG_DMAC_DESCR6_PING_SRC 0x401018c0u
#define CYREG_DMAC_DESCR6_PING_DST 0x401018c4u
#define CYREG_DMAC_DESCR6_PING_CTL 0x401018c8u
#define CYREG_DMAC_DESCR6_PING_STATUS 0x401018ccu
#define CYREG_DMAC_DESCR6_PONG_SRC 0x401018d0u
#define CYREG_DMAC_DESCR6_PONG_DST 0x401018d4u
#define CYREG_DMAC_DESCR6_PONG_CTL 0x401018d8u
#define CYREG_DMAC_DESCR6_PONG_STATUS 0x401018dcu
#define CYDEV_DMAC_DESCR7_BASE 0x401018e0u
#define CYDEV_DMAC_DESCR7_SIZE 0x00000020u
#define CYREG_DMAC_DESCR7_PING_SRC 0x401018e0u
#define CYREG_DMAC_DESCR7_PING_DST 0x401018e4u
#define CYREG_DMAC_DESCR7_PING_CTL 0x401018e8u
#define CYREG_DMAC_DESCR7_PING_STATUS 0x401018ecu
#define CYREG_DMAC_DESCR7_PONG_SRC 0x401018f0u
#define CYREG_DMAC_DESCR7_PONG_DST 0x401018f4u
#define CYREG_DMAC_DESCR7_PONG_CTL 0x401018f8u
#define CYREG_DMAC_DESCR7_PONG_STATUS 0x401018fcu
#define CYDEV_SPCIF_BASE 0x40110000u
#define CYDEV_SPCIF_SIZE 0x00010000u
#define CYREG_SPCIF_GEOMETRY 0x40110000u
#define CYFLD_SPCIF_FLASH__OFFSET 0x00000000u
#define CYFLD_SPCIF_FLASH__SIZE 0x0000000eu
#define CYFLD_SPCIF_SFLASH__OFFSET 0x0000000eu
#define CYFLD_SPCIF_SFLASH__SIZE 0x00000006u
#define CYFLD_SPCIF_NUM_FLASH__OFFSET 0x00000014u
#define CYFLD_SPCIF_NUM_FLASH__SIZE 0x00000002u
#define CYFLD_SPCIF_FLASH_ROW__OFFSET 0x00000016u
#define CYFLD_SPCIF_FLASH_ROW__SIZE 0x00000002u
#define CYFLD_SPCIF_DE_CPD_LP__OFFSET 0x0000001fu
#define CYFLD_SPCIF_DE_CPD_LP__SIZE 0x00000001u
#define CYREG_SPCIF_INTR 0x401107f0u
#define CYFLD_SPCIF_TIMER__OFFSET 0x00000000u
#define CYFLD_SPCIF_TIMER__SIZE 0x00000001u
#define CYREG_SPCIF_INTR_SET 0x401107f4u
#define CYREG_SPCIF_INTR_MASK 0x401107f8u
#define CYREG_SPCIF_INTR_MASKED 0x401107fcu
#define CYDEV_TCPWM_BASE 0x40200000u
#define CYDEV_TCPWM_SIZE 0x00010000u
#define CYREG_TCPWM_CTRL 0x40200000u
#define CYFLD_TCPWM_COUNTER_ENABLED__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_ENABLED__SIZE 0x00000008u
#define CYREG_TCPWM_CMD 0x40200008u
#define CYFLD_TCPWM_COUNTER_CAPTURE__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_CAPTURE__SIZE 0x00000008u
#define CYFLD_TCPWM_COUNTER_RELOAD__OFFSET 0x00000008u
#define CYFLD_TCPWM_COUNTER_RELOAD__SIZE 0x00000008u
#define CYFLD_TCPWM_COUNTER_STOP__OFFSET 0x00000010u
#define CYFLD_TCPWM_COUNTER_STOP__SIZE 0x00000008u
#define CYFLD_TCPWM_COUNTER_START__OFFSET 0x00000018u
#define CYFLD_TCPWM_COUNTER_START__SIZE 0x00000008u
#define CYREG_TCPWM_INTR_CAUSE 0x4020000cu
#define CYFLD_TCPWM_COUNTER_INT__OFFSET 0x00000000u
#define CYFLD_TCPWM_COUNTER_INT__SIZE 0x00000008u
#define CYDEV_TCPWM_CNT0_BASE 0x40200100u
#define CYDEV_TCPWM_CNT0_SIZE 0x00000040u
#define CYREG_TCPWM_CNT0_CTRL 0x40200100u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_CC__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__OFFSET 0x00000001u
#define CYFLD_TCPWM_CNT_AUTO_RELOAD_PERIOD__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_PWM_SYNC_KILL__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__OFFSET 0x00000003u
#define CYFLD_TCPWM_CNT_PWM_STOP_ON_KILL__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_GENERIC__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_GENERIC__SIZE 0x00000008u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY1 0x00000000u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY2 0x00000001u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY4 0x00000002u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY8 0x00000003u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY16 0x00000004u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY32 0x00000005u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY64 0x00000006u
#define CYVAL_TCPWM_CNT_GENERIC_DIVBY128 0x00000007u
#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__OFFSET 0x00000010u
#define CYFLD_TCPWM_CNT_UP_DOWN_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UP 0x00000000u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_DOWN 0x00000001u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN1 0x00000002u
#define CYVAL_TCPWM_CNT_UP_DOWN_MODE_COUNT_UPDN2 0x00000003u
#define CYFLD_TCPWM_CNT_ONE_SHOT__OFFSET 0x00000012u
#define CYFLD_TCPWM_CNT_ONE_SHOT__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__OFFSET 0x00000014u
#define CYFLD_TCPWM_CNT_QUADRATURE_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X1 0x00000000u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X2 0x00000001u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_X4 0x00000002u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_OUT 0x00000001u
#define CYVAL_TCPWM_CNT_QUADRATURE_MODE_INV_COMPL_OUT 0x00000002u
#define CYFLD_TCPWM_CNT_MODE__OFFSET 0x00000018u
#define CYFLD_TCPWM_CNT_MODE__SIZE 0x00000003u
#define CYVAL_TCPWM_CNT_MODE_TIMER 0x00000000u
#define CYVAL_TCPWM_CNT_MODE_CAPTURE 0x00000002u
#define CYVAL_TCPWM_CNT_MODE_QUAD 0x00000003u
#define CYVAL_TCPWM_CNT_MODE_PWM 0x00000004u
#define CYVAL_TCPWM_CNT_MODE_PWM_DT 0x00000005u
#define CYVAL_TCPWM_CNT_MODE_PWM_PR 0x00000006u
#define CYREG_TCPWM_CNT0_STATUS 0x40200104u
#define CYFLD_TCPWM_CNT_DOWN__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_DOWN__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_RUNNING__OFFSET 0x0000001fu
#define CYFLD_TCPWM_CNT_RUNNING__SIZE 0x00000001u
#define CYREG_TCPWM_CNT0_COUNTER 0x40200108u
#define CYFLD_TCPWM_CNT_COUNTER__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_COUNTER__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_CC 0x4020010cu
#define CYFLD_TCPWM_CNT_CC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CC__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_CC_BUFF 0x40200110u
#define CYREG_TCPWM_CNT0_PERIOD 0x40200114u
#define CYFLD_TCPWM_CNT_PERIOD__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_PERIOD__SIZE 0x00000010u
#define CYREG_TCPWM_CNT0_PERIOD_BUFF 0x40200118u
#define CYREG_TCPWM_CNT0_TR_CTRL0 0x40200120u
#define CYFLD_TCPWM_CNT_CAPTURE_SEL__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CAPTURE_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_COUNT_SEL__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_COUNT_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_RELOAD_SEL__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_RELOAD_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_STOP_SEL__OFFSET 0x0000000cu
#define CYFLD_TCPWM_CNT_STOP_SEL__SIZE 0x00000004u
#define CYFLD_TCPWM_CNT_START_SEL__OFFSET 0x00000010u
#define CYFLD_TCPWM_CNT_START_SEL__SIZE 0x00000004u
#define CYREG_TCPWM_CNT0_TR_CTRL1 0x40200124u
#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CAPTURE_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_CAPTURE_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_COUNT_EDGE__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_COUNT_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_COUNT_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_RELOAD_EDGE__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_RELOAD_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_RELOAD_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_STOP_EDGE__OFFSET 0x00000006u
#define CYFLD_TCPWM_CNT_STOP_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_STOP_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_STOP_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_STOP_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_STOP_EDGE_NO_EDGE_DET 0x00000003u
#define CYFLD_TCPWM_CNT_START_EDGE__OFFSET 0x00000008u
#define CYFLD_TCPWM_CNT_START_EDGE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_START_EDGE_RISING_EDGE 0x00000000u
#define CYVAL_TCPWM_CNT_START_EDGE_FALLING_EDGE 0x00000001u
#define CYVAL_TCPWM_CNT_START_EDGE_BOTH_EDGES 0x00000002u
#define CYVAL_TCPWM_CNT_START_EDGE_NO_EDGE_DET 0x00000003u
#define CYREG_TCPWM_CNT0_TR_CTRL2 0x40200128u
#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_CC_MATCH_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_CC_MATCH_MODE_NO_CHANGE 0x00000003u
#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__OFFSET 0x00000002u
#define CYFLD_TCPWM_CNT_OVERFLOW_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_OVERFLOW_MODE_NO_CHANGE 0x00000003u
#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__OFFSET 0x00000004u
#define CYFLD_TCPWM_CNT_UNDERFLOW_MODE__SIZE 0x00000002u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_SET 0x00000000u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_CLEAR 0x00000001u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_INVERT 0x00000002u
#define CYVAL_TCPWM_CNT_UNDERFLOW_MODE_NO_CHANGE 0x00000003u
#define CYREG_TCPWM_CNT0_INTR 0x40200130u
#define CYFLD_TCPWM_CNT_TC__OFFSET 0x00000000u
#define CYFLD_TCPWM_CNT_TC__SIZE 0x00000001u
#define CYFLD_TCPWM_CNT_CC_MATCH__OFFSET 0x00000001u
#define CYFLD_TCPWM_CNT_CC_MATCH__SIZE 0x00000001u
#define CYREG_TCPWM_CNT0_INTR_SET 0x40200134u
#define CYREG_TCPWM_CNT0_INTR_MASK 0x40200138u
#define CYREG_TCPWM_CNT0_INTR_MASKED 0x4020013cu
#define CYDEV_TCPWM_CNT1_BASE 0x40200140u
#define CYDEV_TCPWM_CNT1_SIZE 0x00000040u
#define CYREG_TCPWM_CNT1_CTRL 0x40200140u
#define CYREG_TCPWM_CNT1_STATUS 0x40200144u
#define CYREG_TCPWM_CNT1_COUNTER 0x40200148u
#define CYREG_TCPWM_CNT1_CC 0x4020014cu
#define CYREG_TCPWM_CNT1_CC_BUFF 0x40200150u
#define CYREG_TCPWM_CNT1_PERIOD 0x40200154u
#define CYREG_TCPWM_CNT1_PERIOD_BUFF 0x40200158u
#define CYREG_TCPWM_CNT1_TR_CTRL0 0x40200160u
#define CYREG_TCPWM_CNT1_TR_CTRL1 0x40200164u
#define CYREG_TCPWM_CNT1_TR_CTRL2 0x40200168u
#define CYREG_TCPWM_CNT1_INTR 0x40200170u
#define CYREG_TCPWM_CNT1_INTR_SET 0x40200174u
#define CYREG_TCPWM_CNT1_INTR_MASK 0x40200178u
#define CYREG_TCPWM_CNT1_INTR_MASKED 0x4020017cu
#define CYDEV_TCPWM_CNT2_BASE 0x40200180u
#define CYDEV_TCPWM_CNT2_SIZE 0x00000040u
#define CYREG_TCPWM_CNT2_CTRL 0x40200180u
#define CYREG_TCPWM_CNT2_STATUS 0x40200184u
#define CYREG_TCPWM_CNT2_COUNTER 0x40200188u
#define CYREG_TCPWM_CNT2_CC 0x4020018cu
#define CYREG_TCPWM_CNT2_CC_BUFF 0x40200190u
#define CYREG_TCPWM_CNT2_PERIOD 0x40200194u
#define CYREG_TCPWM_CNT2_PERIOD_BUFF 0x40200198u
#define CYREG_TCPWM_CNT2_TR_CTRL0 0x402001a0u
#define CYREG_TCPWM_CNT2_TR_CTRL1 0x402001a4u
#define CYREG_TCPWM_CNT2_TR_CTRL2 0x402001a8u
#define CYREG_TCPWM_CNT2_INTR 0x402001b0u
#define CYREG_TCPWM_CNT2_INTR_SET 0x402001b4u
#define CYREG_TCPWM_CNT2_INTR_MASK 0x402001b8u
#define CYREG_TCPWM_CNT2_INTR_MASKED 0x402001bcu
#define CYDEV_TCPWM_CNT3_BASE 0x402001c0u
#define CYDEV_TCPWM_CNT3_SIZE 0x00000040u
#define CYREG_TCPWM_CNT3_CTRL 0x402001c0u
#define CYREG_TCPWM_CNT3_STATUS 0x402001c4u
#define CYREG_TCPWM_CNT3_COUNTER 0x402001c8u
#define CYREG_TCPWM_CNT3_CC 0x402001ccu
#define CYREG_TCPWM_CNT3_CC_BUFF 0x402001d0u
#define CYREG_TCPWM_CNT3_PERIOD 0x402001d4u
#define CYREG_TCPWM_CNT3_PERIOD_BUFF 0x402001d8u
#define CYREG_TCPWM_CNT3_TR_CTRL0 0x402001e0u
#define CYREG_TCPWM_CNT3_TR_CTRL1 0x402001e4u
#define CYREG_TCPWM_CNT3_TR_CTRL2 0x402001e8u
#define CYREG_TCPWM_CNT3_INTR 0x402001f0u
#define CYREG_TCPWM_CNT3_INTR_SET 0x402001f4u
#define CYREG_TCPWM_CNT3_INTR_MASK 0x402001f8u
#define CYREG_TCPWM_CNT3_INTR_MASKED 0x402001fcu
#define CYDEV_TCPWM_CNT4_BASE 0x40200200u
#define CYDEV_TCPWM_CNT4_SIZE 0x00000040u
#define CYREG_TCPWM_CNT4_CTRL 0x40200200u
#define CYREG_TCPWM_CNT4_STATUS 0x40200204u
#define CYREG_TCPWM_CNT4_COUNTER 0x40200208u
#define CYREG_TCPWM_CNT4_CC 0x4020020cu
#define CYREG_TCPWM_CNT4_CC_BUFF 0x40200210u
#define CYREG_TCPWM_CNT4_PERIOD 0x40200214u
#define CYREG_TCPWM_CNT4_PERIOD_BUFF 0x40200218u
#define CYREG_TCPWM_CNT4_TR_CTRL0 0x40200220u
#define CYREG_TCPWM_CNT4_TR_CTRL1 0x40200224u
#define CYREG_TCPWM_CNT4_TR_CTRL2 0x40200228u
#define CYREG_TCPWM_CNT4_INTR 0x40200230u
#define CYREG_TCPWM_CNT4_INTR_SET 0x40200234u
#define CYREG_TCPWM_CNT4_INTR_MASK 0x40200238u
#define CYREG_TCPWM_CNT4_INTR_MASKED 0x4020023cu
#define CYDEV_TCPWM_CNT5_BASE 0x40200240u
#define CYDEV_TCPWM_CNT5_SIZE 0x00000040u
#define CYREG_TCPWM_CNT5_CTRL 0x40200240u
#define CYREG_TCPWM_CNT5_STATUS 0x40200244u
#define CYREG_TCPWM_CNT5_COUNTER 0x40200248u
#define CYREG_TCPWM_CNT5_CC 0x4020024cu
#define CYREG_TCPWM_CNT5_CC_BUFF 0x40200250u
#define CYREG_TCPWM_CNT5_PERIOD 0x40200254u
#define CYREG_TCPWM_CNT5_PERIOD_BUFF 0x40200258u
#define CYREG_TCPWM_CNT5_TR_CTRL0 0x40200260u
#define CYREG_TCPWM_CNT5_TR_CTRL1 0x40200264u
#define CYREG_TCPWM_CNT5_TR_CTRL2 0x40200268u
#define CYREG_TCPWM_CNT5_INTR 0x40200270u
#define CYREG_TCPWM_CNT5_INTR_SET 0x40200274u
#define CYREG_TCPWM_CNT5_INTR_MASK 0x40200278u
#define CYREG_TCPWM_CNT5_INTR_MASKED 0x4020027cu
#define CYDEV_TCPWM_CNT6_BASE 0x40200280u
#define CYDEV_TCPWM_CNT6_SIZE 0x00000040u
#define CYREG_TCPWM_CNT6_CTRL 0x40200280u
#define CYREG_TCPWM_CNT6_STATUS 0x40200284u
#define CYREG_TCPWM_CNT6_COUNTER 0x40200288u
#define CYREG_TCPWM_CNT6_CC 0x4020028cu
#define CYREG_TCPWM_CNT6_CC_BUFF 0x40200290u
#define CYREG_TCPWM_CNT6_PERIOD 0x40200294u
#define CYREG_TCPWM_CNT6_PERIOD_BUFF 0x40200298u
#define CYREG_TCPWM_CNT6_TR_CTRL0 0x402002a0u
#define CYREG_TCPWM_CNT6_TR_CTRL1 0x402002a4u
#define CYREG_TCPWM_CNT6_TR_CTRL2 0x402002a8u
#define CYREG_TCPWM_CNT6_INTR 0x402002b0u
#define CYREG_TCPWM_CNT6_INTR_SET 0x402002b4u
#define CYREG_TCPWM_CNT6_INTR_MASK 0x402002b8u
#define CYREG_TCPWM_CNT6_INTR_MASKED 0x402002bcu
#define CYDEV_TCPWM_CNT7_BASE 0x402002c0u
#define CYDEV_TCPWM_CNT7_SIZE 0x00000040u
#define CYREG_TCPWM_CNT7_CTRL 0x402002c0u
#define CYREG_TCPWM_CNT7_STATUS 0x402002c4u
#define CYREG_TCPWM_CNT7_COUNTER 0x402002c8u
#define CYREG_TCPWM_CNT7_CC 0x402002ccu
#define CYREG_TCPWM_CNT7_CC_BUFF 0x402002d0u
#define CYREG_TCPWM_CNT7_PERIOD 0x402002d4u
#define CYREG_TCPWM_CNT7_PERIOD_BUFF 0x402002d8u
#define CYREG_TCPWM_CNT7_TR_CTRL0 0x402002e0u
#define CYREG_TCPWM_CNT7_TR_CTRL1 0x402002e4u
#define CYREG_TCPWM_CNT7_TR_CTRL2 0x402002e8u
#define CYREG_TCPWM_CNT7_INTR 0x402002f0u
#define CYREG_TCPWM_CNT7_INTR_SET 0x402002f4u
#define CYREG_TCPWM_CNT7_INTR_MASK 0x402002f8u
#define CYREG_TCPWM_CNT7_INTR_MASKED 0x402002fcu
#define CYDEV_WCO_BASE 0x40220000u
#define CYDEV_WCO_SIZE 0x00010000u
#define CYREG_WCO_CONFIG 0x40220000u
#define CYFLD_WCO_LPM_EN__OFFSET 0x00000000u
#define CYFLD_WCO_LPM_EN__SIZE 0x00000001u
#define CYFLD_WCO_LPM_AUTO__OFFSET 0x00000001u
#define CYFLD_WCO_LPM_AUTO__SIZE 0x00000001u
#define CYFLD_WCO_EXT_INPUT_EN__OFFSET 0x00000002u
#define CYFLD_WCO_EXT_INPUT_EN__SIZE 0x00000001u
#define CYFLD_WCO_ENBUS__OFFSET 0x00000010u
#define CYFLD_WCO_ENBUS__SIZE 0x00000008u
#define CYFLD_WCO_DPLL_ENABLE__OFFSET 0x0000001eu
#define CYFLD_WCO_DPLL_ENABLE__SIZE 0x00000001u
#define CYFLD_WCO_IP_ENABLE__OFFSET 0x0000001fu
#define CYFLD_WCO_IP_ENABLE__SIZE 0x00000001u
#define CYREG_WCO_STATUS 0x40220004u
#define CYFLD_WCO_OUT_BLNK_A__OFFSET 0x00000000u
#define CYFLD_WCO_OUT_BLNK_A__SIZE 0x00000001u
#define CYREG_WCO_DPLL 0x40220008u
#define CYFLD_WCO_DPLL_MULT__OFFSET 0x00000000u
#define CYFLD_WCO_DPLL_MULT__SIZE 0x0000000bu
#define CYFLD_WCO_DPLL_LF_IGAIN__OFFSET 0x00000010u
#define CYFLD_WCO_DPLL_LF_IGAIN__SIZE 0x00000003u
#define CYFLD_WCO_DPLL_LF_PGAIN__OFFSET 0x00000013u
#define CYFLD_WCO_DPLL_LF_PGAIN__SIZE 0x00000003u
#define CYFLD_WCO_DPLL_LF_LIMIT__OFFSET 0x00000016u
#define CYFLD_WCO_DPLL_LF_LIMIT__SIZE 0x00000008u
#define CYREG_WCO_WDT_CTRLOW 0x40220200u
#define CYFLD_WCO_WDT_CTR0__OFFSET 0x00000000u
#define CYFLD_WCO_WDT_CTR0__SIZE 0x00000010u
#define CYFLD_WCO_WDT_CTR1__OFFSET 0x00000010u
#define CYFLD_WCO_WDT_CTR1__SIZE 0x00000010u
#define CYREG_WCO_WDT_CTRHIGH 0x40220204u
#define CYFLD_WCO_WDT_CTR2__OFFSET 0x00000000u
#define CYFLD_WCO_WDT_CTR2__SIZE 0x00000020u
#define CYREG_WCO_WDT_MATCH 0x40220208u
#define CYFLD_WCO_WDT_MATCH0__OFFSET 0x00000000u
#define CYFLD_WCO_WDT_MATCH0__SIZE 0x00000010u
#define CYFLD_WCO_WDT_MATCH1__OFFSET 0x00000010u
#define CYFLD_WCO_WDT_MATCH1__SIZE 0x00000010u
#define CYREG_WCO_WDT_CONFIG 0x4022020cu
#define CYFLD_WCO_WDT_MODE0__OFFSET 0x00000000u
#define CYFLD_WCO_WDT_MODE0__SIZE 0x00000002u
#define CYVAL_WCO_WDT_MODE0_NOTHING 0x00000000u
#define CYVAL_WCO_WDT_MODE0_INT 0x00000001u
#define CYVAL_WCO_WDT_MODE0_RESET 0x00000002u
#define CYVAL_WCO_WDT_MODE0_INT_THEN_RESET 0x00000003u
#define CYFLD_WCO_WDT_CLEAR0__OFFSET 0x00000002u
#define CYFLD_WCO_WDT_CLEAR0__SIZE 0x00000001u
#define CYFLD_WCO_WDT_CASCADE0_1__OFFSET 0x00000003u
#define CYFLD_WCO_WDT_CASCADE0_1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_MODE1__OFFSET 0x00000008u
#define CYFLD_WCO_WDT_MODE1__SIZE 0x00000002u
#define CYVAL_WCO_WDT_MODE1_NOTHING 0x00000000u
#define CYVAL_WCO_WDT_MODE1_INT 0x00000001u
#define CYVAL_WCO_WDT_MODE1_RESET 0x00000002u
#define CYVAL_WCO_WDT_MODE1_INT_THEN_RESET 0x00000003u
#define CYFLD_WCO_WDT_CLEAR1__OFFSET 0x0000000au
#define CYFLD_WCO_WDT_CLEAR1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_CASCADE1_2__OFFSET 0x0000000bu
#define CYFLD_WCO_WDT_CASCADE1_2__SIZE 0x00000001u
#define CYFLD_WCO_WDT_MODE2__OFFSET 0x00000010u
#define CYFLD_WCO_WDT_MODE2__SIZE 0x00000001u
#define CYVAL_WCO_WDT_MODE2_NOTHING 0x00000000u
#define CYVAL_WCO_WDT_MODE2_INT 0x00000001u
#define CYFLD_WCO_WDT_BITS2__OFFSET 0x00000018u
#define CYFLD_WCO_WDT_BITS2__SIZE 0x00000005u
#define CYFLD_WCO_LFCLK_SEL__OFFSET 0x0000001eu
#define CYFLD_WCO_LFCLK_SEL__SIZE 0x00000002u
#define CYREG_WCO_WDT_CONTROL 0x40220210u
#define CYFLD_WCO_WDT_ENABLE0__OFFSET 0x00000000u
#define CYFLD_WCO_WDT_ENABLE0__SIZE 0x00000001u
#define CYFLD_WCO_WDT_ENABLED0__OFFSET 0x00000001u
#define CYFLD_WCO_WDT_ENABLED0__SIZE 0x00000001u
#define CYFLD_WCO_WDT_INT0__OFFSET 0x00000002u
#define CYFLD_WCO_WDT_INT0__SIZE 0x00000001u
#define CYFLD_WCO_WDT_RESET0__OFFSET 0x00000003u
#define CYFLD_WCO_WDT_RESET0__SIZE 0x00000001u
#define CYFLD_WCO_WDT_ENABLE1__OFFSET 0x00000008u
#define CYFLD_WCO_WDT_ENABLE1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_ENABLED1__OFFSET 0x00000009u
#define CYFLD_WCO_WDT_ENABLED1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_INT1__OFFSET 0x0000000au
#define CYFLD_WCO_WDT_INT1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_RESET1__OFFSET 0x0000000bu
#define CYFLD_WCO_WDT_RESET1__SIZE 0x00000001u
#define CYFLD_WCO_WDT_ENABLE2__OFFSET 0x00000010u
#define CYFLD_WCO_WDT_ENABLE2__SIZE 0x00000001u
#define CYFLD_WCO_WDT_ENABLED2__OFFSET 0x00000011u
#define CYFLD_WCO_WDT_ENABLED2__SIZE 0x00000001u
#define CYFLD_WCO_WDT_INT2__OFFSET 0x00000012u
#define CYFLD_WCO_WDT_INT2__SIZE 0x00000001u
#define CYFLD_WCO_WDT_RESET2__OFFSET 0x00000013u
#define CYFLD_WCO_WDT_RESET2__SIZE 0x00000001u
#define CYREG_WCO_WDT_CLKEN 0x40220214u
#define CYFLD_WCO_CLK_WCO_EN_FOR_WDT__OFFSET 0x00000000u
#define CYFLD_WCO_CLK_WCO_EN_FOR_WDT__SIZE 0x00000001u
#define CYFLD_WCO_CLK_ILO_EN_FOR_WDT__OFFSET 0x00000001u
#define CYFLD_WCO_CLK_ILO_EN_FOR_WDT__SIZE 0x00000001u
#define CYREG_WCO_TRIM 0x40220f00u
#define CYFLD_WCO_XGM__OFFSET 0x00000000u
#define CYFLD_WCO_XGM__SIZE 0x00000003u
#define CYFLD_WCO_LPM_GM__OFFSET 0x00000004u
#define CYFLD_WCO_LPM_GM__SIZE 0x00000002u
#define CYDEV_SCB0_BASE 0x40240000u
#define CYDEV_SCB0_SIZE 0x00010000u
#define CYREG_SCB0_CTRL 0x40240000u
#define CYFLD_SCB_OVS__OFFSET 0x00000000u
#define CYFLD_SCB_OVS__SIZE 0x00000004u
#define CYFLD_SCB_EC_AM_MODE__OFFSET 0x00000008u
#define CYFLD_SCB_EC_AM_MODE__SIZE 0x00000001u
#define CYFLD_SCB_EC_OP_MODE__OFFSET 0x00000009u
#define CYFLD_SCB_EC_OP_MODE__SIZE 0x00000001u
#define CYFLD_SCB_EZ_MODE__OFFSET 0x0000000au
#define CYFLD_SCB_EZ_MODE__SIZE 0x00000001u
#define CYFLD_SCB_BYTE_MODE__OFFSET 0x0000000bu
#define CYFLD_SCB_BYTE_MODE__SIZE 0x00000001u
#define CYFLD_SCB_ADDR_ACCEPT__OFFSET 0x00000010u
#define CYFLD_SCB_ADDR_ACCEPT__SIZE 0x00000001u
#define CYFLD_SCB_BLOCK__OFFSET 0x00000011u
#define CYFLD_SCB_BLOCK__SIZE 0x00000001u
#define CYFLD_SCB_MODE__OFFSET 0x00000018u
#define CYFLD_SCB_MODE__SIZE 0x00000002u
#define CYVAL_SCB_MODE_I2C 0x00000000u
#define CYVAL_SCB_MODE_SPI 0x00000001u
#define CYVAL_SCB_MODE_UART 0x00000002u
#define CYFLD_SCB_ENABLED__OFFSET 0x0000001fu
#define CYFLD_SCB_ENABLED__SIZE 0x00000001u
#define CYREG_SCB0_STATUS 0x40240004u
#define CYFLD_SCB_EC_BUSY__OFFSET 0x00000000u
#define CYFLD_SCB_EC_BUSY__SIZE 0x00000001u
#define CYREG_SCB0_SPI_CTRL 0x40240020u
#define CYFLD_SCB_CONTINUOUS__OFFSET 0x00000000u
#define CYFLD_SCB_CONTINUOUS__SIZE 0x00000001u
#define CYFLD_SCB_SELECT_PRECEDE__OFFSET 0x00000001u
#define CYFLD_SCB_SELECT_PRECEDE__SIZE 0x00000001u
#define CYFLD_SCB_CPHA__OFFSET 0x00000002u
#define CYFLD_SCB_CPHA__SIZE 0x00000001u
#define CYFLD_SCB_CPOL__OFFSET 0x00000003u
#define CYFLD_SCB_CPOL__SIZE 0x00000001u
#define CYFLD_SCB_LATE_MISO_SAMPLE__OFFSET 0x00000004u
#define CYFLD_SCB_LATE_MISO_SAMPLE__SIZE 0x00000001u
#define CYFLD_SCB_SCLK_CONTINUOUS__OFFSET 0x00000005u
#define CYFLD_SCB_SCLK_CONTINUOUS__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY0__OFFSET 0x00000008u
#define CYFLD_SCB_SSEL_POLARITY0__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY1__OFFSET 0x00000009u
#define CYFLD_SCB_SSEL_POLARITY1__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY2__OFFSET 0x0000000au
#define CYFLD_SCB_SSEL_POLARITY2__SIZE 0x00000001u
#define CYFLD_SCB_SSEL_POLARITY3__OFFSET 0x0000000bu
#define CYFLD_SCB_SSEL_POLARITY3__SIZE 0x00000001u
#define CYFLD_SCB_LOOPBACK__OFFSET 0x00000010u
#define CYFLD_SCB_LOOPBACK__SIZE 0x00000001u
#define CYFLD_SCB_SLAVE_SELECT__OFFSET 0x0000001au
#define CYFLD_SCB_SLAVE_SELECT__SIZE 0x00000002u
#define CYFLD_SCB_MASTER_MODE__OFFSET 0x0000001fu
#define CYFLD_SCB_MASTER_MODE__SIZE 0x00000001u
#define CYREG_SCB0_SPI_STATUS 0x40240024u
#define CYFLD_SCB_BUS_BUSY__OFFSET 0x00000000u
#define CYFLD_SCB_BUS_BUSY__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EC_BUSY__OFFSET 0x00000001u
#define CYFLD_SCB_SPI_EC_BUSY__SIZE 0x00000001u
#define CYFLD_SCB_CURR_EZ_ADDR__OFFSET 0x00000008u
#define CYFLD_SCB_CURR_EZ_ADDR__SIZE 0x00000008u
#define CYFLD_SCB_BASE_EZ_ADDR__OFFSET 0x00000010u
#define CYFLD_SCB_BASE_EZ_ADDR__SIZE 0x00000008u
#define CYREG_SCB0_UART_CTRL 0x40240040u
#define CYREG_SCB0_UART_TX_CTRL 0x40240044u
#define CYFLD_SCB_STOP_BITS__OFFSET 0x00000000u
#define CYFLD_SCB_STOP_BITS__SIZE 0x00000003u
#define CYFLD_SCB_PARITY__OFFSET 0x00000004u
#define CYFLD_SCB_PARITY__SIZE 0x00000001u
#define CYFLD_SCB_PARITY_ENABLED__OFFSET 0x00000005u
#define CYFLD_SCB_PARITY_ENABLED__SIZE 0x00000001u
#define CYFLD_SCB_RETRY_ON_NACK__OFFSET 0x00000008u
#define CYFLD_SCB_RETRY_ON_NACK__SIZE 0x00000001u
#define CYREG_SCB0_UART_RX_CTRL 0x40240048u
#define CYFLD_SCB_POLARITY__OFFSET 0x00000006u
#define CYFLD_SCB_POLARITY__SIZE 0x00000001u
#define CYFLD_SCB_DROP_ON_PARITY_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_DROP_ON_PARITY_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_DROP_ON_FRAME_ERROR__OFFSET 0x00000009u
#define CYFLD_SCB_DROP_ON_FRAME_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_MP_MODE__OFFSET 0x0000000au
#define CYFLD_SCB_MP_MODE__SIZE 0x00000001u
#define CYFLD_SCB_LIN_MODE__OFFSET 0x0000000cu
#define CYFLD_SCB_LIN_MODE__SIZE 0x00000001u
#define CYFLD_SCB_SKIP_START__OFFSET 0x0000000du
#define CYFLD_SCB_SKIP_START__SIZE 0x00000001u
#define CYFLD_SCB_BREAK_WIDTH__OFFSET 0x00000010u
#define CYFLD_SCB_BREAK_WIDTH__SIZE 0x00000004u
#define CYREG_SCB0_UART_RX_STATUS 0x4024004cu
#define CYFLD_SCB_BR_COUNTER__OFFSET 0x00000000u
#define CYFLD_SCB_BR_COUNTER__SIZE 0x0000000cu
#define CYREG_SCB0_UART_FLOW_CTRL 0x40240050u
#define CYFLD_SCB_TRIGGER_LEVEL__OFFSET 0x00000000u
#define CYFLD_SCB_TRIGGER_LEVEL__SIZE 0x00000004u
#define CYFLD_SCB_RTS_POLARITY__OFFSET 0x00000010u
#define CYFLD_SCB_RTS_POLARITY__SIZE 0x00000001u
#define CYFLD_SCB_CTS_POLARITY__OFFSET 0x00000018u
#define CYFLD_SCB_CTS_POLARITY__SIZE 0x00000001u
#define CYFLD_SCB_CTS_ENABLED__OFFSET 0x00000019u
#define CYFLD_SCB_CTS_ENABLED__SIZE 0x00000001u
#define CYREG_SCB0_I2C_CTRL 0x40240060u
#define CYFLD_SCB_HIGH_PHASE_OVS__OFFSET 0x00000000u
#define CYFLD_SCB_HIGH_PHASE_OVS__SIZE 0x00000004u
#define CYFLD_SCB_LOW_PHASE_OVS__OFFSET 0x00000004u
#define CYFLD_SCB_LOW_PHASE_OVS__SIZE 0x00000004u
#define CYFLD_SCB_M_READY_DATA_ACK__OFFSET 0x00000008u
#define CYFLD_SCB_M_READY_DATA_ACK__SIZE 0x00000001u
#define CYFLD_SCB_M_NOT_READY_DATA_NACK__OFFSET 0x00000009u
#define CYFLD_SCB_M_NOT_READY_DATA_NACK__SIZE 0x00000001u
#define CYFLD_SCB_S_GENERAL_IGNORE__OFFSET 0x0000000bu
#define CYFLD_SCB_S_GENERAL_IGNORE__SIZE 0x00000001u
#define CYFLD_SCB_S_READY_ADDR_ACK__OFFSET 0x0000000cu
#define CYFLD_SCB_S_READY_ADDR_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_READY_DATA_ACK__OFFSET 0x0000000du
#define CYFLD_SCB_S_READY_DATA_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__OFFSET 0x0000000eu
#define CYFLD_SCB_S_NOT_READY_ADDR_NACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NOT_READY_DATA_NACK__OFFSET 0x0000000fu
#define CYFLD_SCB_S_NOT_READY_DATA_NACK__SIZE 0x00000001u
#define CYFLD_SCB_SLAVE_MODE__OFFSET 0x0000001eu
#define CYFLD_SCB_SLAVE_MODE__SIZE 0x00000001u
#define CYREG_SCB0_I2C_STATUS 0x40240064u
#define CYFLD_SCB_I2C_EC_BUSY__OFFSET 0x00000001u
#define CYFLD_SCB_I2C_EC_BUSY__SIZE 0x00000001u
#define CYFLD_SCB_S_READ__OFFSET 0x00000004u
#define CYFLD_SCB_S_READ__SIZE 0x00000001u
#define CYFLD_SCB_M_READ__OFFSET 0x00000005u
#define CYFLD_SCB_M_READ__SIZE 0x00000001u
#define CYREG_SCB0_I2C_M_CMD 0x40240068u
#define CYFLD_SCB_M_START__OFFSET 0x00000000u
#define CYFLD_SCB_M_START__SIZE 0x00000001u
#define CYFLD_SCB_M_START_ON_IDLE__OFFSET 0x00000001u
#define CYFLD_SCB_M_START_ON_IDLE__SIZE 0x00000001u
#define CYFLD_SCB_M_ACK__OFFSET 0x00000002u
#define CYFLD_SCB_M_ACK__SIZE 0x00000001u
#define CYFLD_SCB_M_NACK__OFFSET 0x00000003u
#define CYFLD_SCB_M_NACK__SIZE 0x00000001u
#define CYFLD_SCB_M_STOP__OFFSET 0x00000004u
#define CYFLD_SCB_M_STOP__SIZE 0x00000001u
#define CYREG_SCB0_I2C_S_CMD 0x4024006cu
#define CYFLD_SCB_S_ACK__OFFSET 0x00000000u
#define CYFLD_SCB_S_ACK__SIZE 0x00000001u
#define CYFLD_SCB_S_NACK__OFFSET 0x00000001u
#define CYFLD_SCB_S_NACK__SIZE 0x00000001u
#define CYREG_SCB0_I2C_CFG 0x40240070u
#define CYFLD_SCB_SDA_IN_FILT_TRIM__OFFSET 0x00000000u
#define CYFLD_SCB_SDA_IN_FILT_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_IN_FILT_SEL__OFFSET 0x00000004u
#define CYFLD_SCB_SDA_IN_FILT_SEL__SIZE 0x00000001u
#define CYFLD_SCB_SCL_IN_FILT_TRIM__OFFSET 0x00000008u
#define CYFLD_SCB_SCL_IN_FILT_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SCL_IN_FILT_SEL__OFFSET 0x0000000cu
#define CYFLD_SCB_SCL_IN_FILT_SEL__SIZE 0x00000001u
#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__OFFSET 0x00000010u
#define CYFLD_SCB_SDA_OUT_FILT0_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__OFFSET 0x00000012u
#define CYFLD_SCB_SDA_OUT_FILT1_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__OFFSET 0x00000014u
#define CYFLD_SCB_SDA_OUT_FILT2_TRIM__SIZE 0x00000002u
#define CYFLD_SCB_SDA_OUT_FILT_SEL__OFFSET 0x0000001cu
#define CYFLD_SCB_SDA_OUT_FILT_SEL__SIZE 0x00000002u
#define CYREG_SCB0_TX_CTRL 0x40240200u
#define CYFLD_SCB_DATA_WIDTH__OFFSET 0x00000000u
#define CYFLD_SCB_DATA_WIDTH__SIZE 0x00000004u
#define CYFLD_SCB_MSB_FIRST__OFFSET 0x00000008u
#define CYFLD_SCB_MSB_FIRST__SIZE 0x00000001u
#define CYREG_SCB0_TX_FIFO_CTRL 0x40240204u
#define CYFLD_SCB_CLEAR__OFFSET 0x00000010u
#define CYFLD_SCB_CLEAR__SIZE 0x00000001u
#define CYFLD_SCB_FREEZE__OFFSET 0x00000011u
#define CYFLD_SCB_FREEZE__SIZE 0x00000001u
#define CYREG_SCB0_TX_FIFO_STATUS 0x40240208u
#define CYFLD_SCB_USED__OFFSET 0x00000000u
#define CYFLD_SCB_USED__SIZE 0x00000005u
#define CYFLD_SCB_SR_VALID__OFFSET 0x0000000fu
#define CYFLD_SCB_SR_VALID__SIZE 0x00000001u
#define CYFLD_SCB_RD_PTR__OFFSET 0x00000010u
#define CYFLD_SCB_RD_PTR__SIZE 0x00000004u
#define CYFLD_SCB_WR_PTR__OFFSET 0x00000018u
#define CYFLD_SCB_WR_PTR__SIZE 0x00000004u
#define CYREG_SCB0_TX_FIFO_WR 0x40240240u
#define CYFLD_SCB_DATA__OFFSET 0x00000000u
#define CYFLD_SCB_DATA__SIZE 0x00000010u
#define CYREG_SCB0_RX_CTRL 0x40240300u
#define CYFLD_SCB_MEDIAN__OFFSET 0x00000009u
#define CYFLD_SCB_MEDIAN__SIZE 0x00000001u
#define CYREG_SCB0_RX_FIFO_CTRL 0x40240304u
#define CYREG_SCB0_RX_FIFO_STATUS 0x40240308u
#define CYREG_SCB0_RX_MATCH 0x40240310u
#define CYFLD_SCB_ADDR__OFFSET 0x00000000u
#define CYFLD_SCB_ADDR__SIZE 0x00000008u
#define CYFLD_SCB_MASK__OFFSET 0x00000010u
#define CYFLD_SCB_MASK__SIZE 0x00000008u
#define CYREG_SCB0_RX_FIFO_RD 0x40240340u
#define CYREG_SCB0_RX_FIFO_RD_SILENT 0x40240344u
#define CYREG_SCB0_EZ_DATA0 0x40240400u
#define CYFLD_SCB_EZ_DATA__OFFSET 0x00000000u
#define CYFLD_SCB_EZ_DATA__SIZE 0x00000008u
#define CYREG_SCB0_EZ_DATA1 0x40240404u
#define CYREG_SCB0_EZ_DATA2 0x40240408u
#define CYREG_SCB0_EZ_DATA3 0x4024040cu
#define CYREG_SCB0_EZ_DATA4 0x40240410u
#define CYREG_SCB0_EZ_DATA5 0x40240414u
#define CYREG_SCB0_EZ_DATA6 0x40240418u
#define CYREG_SCB0_EZ_DATA7 0x4024041cu
#define CYREG_SCB0_EZ_DATA8 0x40240420u
#define CYREG_SCB0_EZ_DATA9 0x40240424u
#define CYREG_SCB0_EZ_DATA10 0x40240428u
#define CYREG_SCB0_EZ_DATA11 0x4024042cu
#define CYREG_SCB0_EZ_DATA12 0x40240430u
#define CYREG_SCB0_EZ_DATA13 0x40240434u
#define CYREG_SCB0_EZ_DATA14 0x40240438u
#define CYREG_SCB0_EZ_DATA15 0x4024043cu
#define CYREG_SCB0_EZ_DATA16 0x40240440u
#define CYREG_SCB0_EZ_DATA17 0x40240444u
#define CYREG_SCB0_EZ_DATA18 0x40240448u
#define CYREG_SCB0_EZ_DATA19 0x4024044cu
#define CYREG_SCB0_EZ_DATA20 0x40240450u
#define CYREG_SCB0_EZ_DATA21 0x40240454u
#define CYREG_SCB0_EZ_DATA22 0x40240458u
#define CYREG_SCB0_EZ_DATA23 0x4024045cu
#define CYREG_SCB0_EZ_DATA24 0x40240460u
#define CYREG_SCB0_EZ_DATA25 0x40240464u
#define CYREG_SCB0_EZ_DATA26 0x40240468u
#define CYREG_SCB0_EZ_DATA27 0x4024046cu
#define CYREG_SCB0_EZ_DATA28 0x40240470u
#define CYREG_SCB0_EZ_DATA29 0x40240474u
#define CYREG_SCB0_EZ_DATA30 0x40240478u
#define CYREG_SCB0_EZ_DATA31 0x4024047cu
#define CYREG_SCB0_INTR_CAUSE 0x40240e00u
#define CYFLD_SCB_M__OFFSET 0x00000000u
#define CYFLD_SCB_M__SIZE 0x00000001u
#define CYFLD_SCB_S__OFFSET 0x00000001u
#define CYFLD_SCB_S__SIZE 0x00000001u
#define CYFLD_SCB_TX__OFFSET 0x00000002u
#define CYFLD_SCB_TX__SIZE 0x00000001u
#define CYFLD_SCB_RX__OFFSET 0x00000003u
#define CYFLD_SCB_RX__SIZE 0x00000001u
#define CYFLD_SCB_I2C_EC__OFFSET 0x00000004u
#define CYFLD_SCB_I2C_EC__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EC__OFFSET 0x00000005u
#define CYFLD_SCB_SPI_EC__SIZE 0x00000001u
#define CYREG_SCB0_INTR_I2C_EC 0x40240e80u
#define CYFLD_SCB_WAKE_UP__OFFSET 0x00000000u
#define CYFLD_SCB_WAKE_UP__SIZE 0x00000001u
#define CYFLD_SCB_EZ_STOP__OFFSET 0x00000001u
#define CYFLD_SCB_EZ_STOP__SIZE 0x00000001u
#define CYFLD_SCB_EZ_WRITE_STOP__OFFSET 0x00000002u
#define CYFLD_SCB_EZ_WRITE_STOP__SIZE 0x00000001u
#define CYFLD_SCB_EZ_READ_STOP__OFFSET 0x00000003u
#define CYFLD_SCB_EZ_READ_STOP__SIZE 0x00000001u
#define CYREG_SCB0_INTR_I2C_EC_MASK 0x40240e88u
#define CYREG_SCB0_INTR_I2C_EC_MASKED 0x40240e8cu
#define CYREG_SCB0_INTR_SPI_EC 0x40240ec0u
#define CYREG_SCB0_INTR_SPI_EC_MASK 0x40240ec8u
#define CYREG_SCB0_INTR_SPI_EC_MASKED 0x40240eccu
#define CYREG_SCB0_INTR_M 0x40240f00u
#define CYFLD_SCB_I2C_ARB_LOST__OFFSET 0x00000000u
#define CYFLD_SCB_I2C_ARB_LOST__SIZE 0x00000001u
#define CYFLD_SCB_I2C_NACK__OFFSET 0x00000001u
#define CYFLD_SCB_I2C_NACK__SIZE 0x00000001u
#define CYFLD_SCB_I2C_ACK__OFFSET 0x00000002u
#define CYFLD_SCB_I2C_ACK__SIZE 0x00000001u
#define CYFLD_SCB_I2C_STOP__OFFSET 0x00000004u
#define CYFLD_SCB_I2C_STOP__SIZE 0x00000001u
#define CYFLD_SCB_I2C_BUS_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_I2C_BUS_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_SPI_DONE__OFFSET 0x00000009u
#define CYFLD_SCB_SPI_DONE__SIZE 0x00000001u
#define CYREG_SCB0_INTR_M_SET 0x40240f04u
#define CYREG_SCB0_INTR_M_MASK 0x40240f08u
#define CYREG_SCB0_INTR_M_MASKED 0x40240f0cu
#define CYREG_SCB0_INTR_S 0x40240f40u
#define CYFLD_SCB_I2C_WRITE_STOP__OFFSET 0x00000003u
#define CYFLD_SCB_I2C_WRITE_STOP__SIZE 0x00000001u
#define CYFLD_SCB_I2C_START__OFFSET 0x00000005u
#define CYFLD_SCB_I2C_START__SIZE 0x00000001u
#define CYFLD_SCB_I2C_ADDR_MATCH__OFFSET 0x00000006u
#define CYFLD_SCB_I2C_ADDR_MATCH__SIZE 0x00000001u
#define CYFLD_SCB_I2C_GENERAL__OFFSET 0x00000007u
#define CYFLD_SCB_I2C_GENERAL__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EZ_WRITE_STOP__OFFSET 0x00000009u
#define CYFLD_SCB_SPI_EZ_WRITE_STOP__SIZE 0x00000001u
#define CYFLD_SCB_SPI_EZ_STOP__OFFSET 0x0000000au
#define CYFLD_SCB_SPI_EZ_STOP__SIZE 0x00000001u
#define CYFLD_SCB_SPI_BUS_ERROR__OFFSET 0x0000000bu
#define CYFLD_SCB_SPI_BUS_ERROR__SIZE 0x00000001u
#define CYREG_SCB0_INTR_S_SET 0x40240f44u
#define CYREG_SCB0_INTR_S_MASK 0x40240f48u
#define CYREG_SCB0_INTR_S_MASKED 0x40240f4cu
#define CYREG_SCB0_INTR_TX 0x40240f80u
#define CYFLD_SCB_TRIGGER__OFFSET 0x00000000u
#define CYFLD_SCB_TRIGGER__SIZE 0x00000001u
#define CYFLD_SCB_NOT_FULL__OFFSET 0x00000001u
#define CYFLD_SCB_NOT_FULL__SIZE 0x00000001u
#define CYFLD_SCB_EMPTY__OFFSET 0x00000004u
#define CYFLD_SCB_EMPTY__SIZE 0x00000001u
#define CYFLD_SCB_OVERFLOW__OFFSET 0x00000005u
#define CYFLD_SCB_OVERFLOW__SIZE 0x00000001u
#define CYFLD_SCB_UNDERFLOW__OFFSET 0x00000006u
#define CYFLD_SCB_UNDERFLOW__SIZE 0x00000001u
#define CYFLD_SCB_BLOCKED__OFFSET 0x00000007u
#define CYFLD_SCB_BLOCKED__SIZE 0x00000001u
#define CYFLD_SCB_UART_NACK__OFFSET 0x00000008u
#define CYFLD_SCB_UART_NACK__SIZE 0x00000001u
#define CYFLD_SCB_UART_DONE__OFFSET 0x00000009u
#define CYFLD_SCB_UART_DONE__SIZE 0x00000001u
#define CYFLD_SCB_UART_ARB_LOST__OFFSET 0x0000000au
#define CYFLD_SCB_UART_ARB_LOST__SIZE 0x00000001u
#define CYREG_SCB0_INTR_TX_SET 0x40240f84u
#define CYREG_SCB0_INTR_TX_MASK 0x40240f88u
#define CYREG_SCB0_INTR_TX_MASKED 0x40240f8cu
#define CYREG_SCB0_INTR_RX 0x40240fc0u
#define CYFLD_SCB_NOT_EMPTY__OFFSET 0x00000002u
#define CYFLD_SCB_NOT_EMPTY__SIZE 0x00000001u
#define CYFLD_SCB_FULL__OFFSET 0x00000003u
#define CYFLD_SCB_FULL__SIZE 0x00000001u
#define CYFLD_SCB_FRAME_ERROR__OFFSET 0x00000008u
#define CYFLD_SCB_FRAME_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_PARITY_ERROR__OFFSET 0x00000009u
#define CYFLD_SCB_PARITY_ERROR__SIZE 0x00000001u
#define CYFLD_SCB_BAUD_DETECT__OFFSET 0x0000000au
#define CYFLD_SCB_BAUD_DETECT__SIZE 0x00000001u
#define CYFLD_SCB_BREAK_DETECT__OFFSET 0x0000000bu
#define CYFLD_SCB_BREAK_DETECT__SIZE 0x00000001u
#define CYREG_SCB0_INTR_RX_SET 0x40240fc4u
#define CYREG_SCB0_INTR_RX_MASK 0x40240fc8u
#define CYREG_SCB0_INTR_RX_MASKED 0x40240fccu
#define CYDEV_SCB1_BASE 0x40250000u
#define CYDEV_SCB1_SIZE 0x00010000u
#define CYREG_SCB1_CTRL 0x40250000u
#define CYREG_SCB1_STATUS 0x40250004u
#define CYREG_SCB1_SPI_CTRL 0x40250020u
#define CYREG_SCB1_SPI_STATUS 0x40250024u
#define CYREG_SCB1_UART_CTRL 0x40250040u
#define CYREG_SCB1_UART_TX_CTRL 0x40250044u
#define CYREG_SCB1_UART_RX_CTRL 0x40250048u
#define CYREG_SCB1_UART_RX_STATUS 0x4025004cu
#define CYREG_SCB1_UART_FLOW_CTRL 0x40250050u
#define CYREG_SCB1_I2C_CTRL 0x40250060u
#define CYREG_SCB1_I2C_STATUS 0x40250064u
#define CYREG_SCB1_I2C_M_CMD 0x40250068u
#define CYREG_SCB1_I2C_S_CMD 0x4025006cu
#define CYREG_SCB1_I2C_CFG 0x40250070u
#define CYREG_SCB1_TX_CTRL 0x40250200u
#define CYREG_SCB1_TX_FIFO_CTRL 0x40250204u
#define CYREG_SCB1_TX_FIFO_STATUS 0x40250208u
#define CYREG_SCB1_TX_FIFO_WR 0x40250240u
#define CYREG_SCB1_RX_CTRL 0x40250300u
#define CYREG_SCB1_RX_FIFO_CTRL 0x40250304u
#define CYREG_SCB1_RX_FIFO_STATUS 0x40250308u
#define CYREG_SCB1_RX_MATCH 0x40250310u
#define CYREG_SCB1_RX_FIFO_RD 0x40250340u
#define CYREG_SCB1_RX_FIFO_RD_SILENT 0x40250344u
#define CYREG_SCB1_EZ_DATA0 0x40250400u
#define CYREG_SCB1_EZ_DATA1 0x40250404u
#define CYREG_SCB1_EZ_DATA2 0x40250408u
#define CYREG_SCB1_EZ_DATA3 0x4025040cu
#define CYREG_SCB1_EZ_DATA4 0x40250410u
#define CYREG_SCB1_EZ_DATA5 0x40250414u
#define CYREG_SCB1_EZ_DATA6 0x40250418u
#define CYREG_SCB1_EZ_DATA7 0x4025041cu
#define CYREG_SCB1_EZ_DATA8 0x40250420u
#define CYREG_SCB1_EZ_DATA9 0x40250424u
#define CYREG_SCB1_EZ_DATA10 0x40250428u
#define CYREG_SCB1_EZ_DATA11 0x4025042cu
#define CYREG_SCB1_EZ_DATA12 0x40250430u
#define CYREG_SCB1_EZ_DATA13 0x40250434u
#define CYREG_SCB1_EZ_DATA14 0x40250438u
#define CYREG_SCB1_EZ_DATA15 0x4025043cu
#define CYREG_SCB1_EZ_DATA16 0x40250440u
#define CYREG_SCB1_EZ_DATA17 0x40250444u
#define CYREG_SCB1_EZ_DATA18 0x40250448u
#define CYREG_SCB1_EZ_DATA19 0x4025044cu
#define CYREG_SCB1_EZ_DATA20 0x40250450u
#define CYREG_SCB1_EZ_DATA21 0x40250454u
#define CYREG_SCB1_EZ_DATA22 0x40250458u
#define CYREG_SCB1_EZ_DATA23 0x4025045cu
#define CYREG_SCB1_EZ_DATA24 0x40250460u
#define CYREG_SCB1_EZ_DATA25 0x40250464u
#define CYREG_SCB1_EZ_DATA26 0x40250468u
#define CYREG_SCB1_EZ_DATA27 0x4025046cu
#define CYREG_SCB1_EZ_DATA28 0x40250470u
#define CYREG_SCB1_EZ_DATA29 0x40250474u
#define CYREG_SCB1_EZ_DATA30 0x40250478u
#define CYREG_SCB1_EZ_DATA31 0x4025047cu
#define CYREG_SCB1_INTR_CAUSE 0x40250e00u
#define CYREG_SCB1_INTR_I2C_EC 0x40250e80u
#define CYREG_SCB1_INTR_I2C_EC_MASK 0x40250e88u
#define CYREG_SCB1_INTR_I2C_EC_MASKED 0x40250e8cu
#define CYREG_SCB1_INTR_SPI_EC 0x40250ec0u
#define CYREG_SCB1_INTR_SPI_EC_MASK 0x40250ec8u
#define CYREG_SCB1_INTR_SPI_EC_MASKED 0x40250eccu
#define CYREG_SCB1_INTR_M 0x40250f00u
#define CYREG_SCB1_INTR_M_SET 0x40250f04u
#define CYREG_SCB1_INTR_M_MASK 0x40250f08u
#define CYREG_SCB1_INTR_M_MASKED 0x40250f0cu
#define CYREG_SCB1_INTR_S 0x40250f40u
#define CYREG_SCB1_INTR_S_SET 0x40250f44u
#define CYREG_SCB1_INTR_S_MASK 0x40250f48u
#define CYREG_SCB1_INTR_S_MASKED 0x40250f4cu
#define CYREG_SCB1_INTR_TX 0x40250f80u
#define CYREG_SCB1_INTR_TX_SET 0x40250f84u
#define CYREG_SCB1_INTR_TX_MASK 0x40250f88u
#define CYREG_SCB1_INTR_TX_MASKED 0x40250f8cu
#define CYREG_SCB1_INTR_RX 0x40250fc0u
#define CYREG_SCB1_INTR_RX_SET 0x40250fc4u
#define CYREG_SCB1_INTR_RX_MASK 0x40250fc8u
#define CYREG_SCB1_INTR_RX_MASKED 0x40250fccu
#define CYDEV_SCB2_BASE 0x40260000u
#define CYDEV_SCB2_SIZE 0x00010000u
#define CYREG_SCB2_CTRL 0x40260000u
#define CYREG_SCB2_STATUS 0x40260004u
#define CYREG_SCB2_SPI_CTRL 0x40260020u
#define CYREG_SCB2_SPI_STATUS 0x40260024u
#define CYREG_SCB2_UART_CTRL 0x40260040u
#define CYREG_SCB2_UART_TX_CTRL 0x40260044u
#define CYREG_SCB2_UART_RX_CTRL 0x40260048u
#define CYREG_SCB2_UART_RX_STATUS 0x4026004cu
#define CYREG_SCB2_UART_FLOW_CTRL 0x40260050u
#define CYREG_SCB2_I2C_CTRL 0x40260060u
#define CYREG_SCB2_I2C_STATUS 0x40260064u
#define CYREG_SCB2_I2C_M_CMD 0x40260068u
#define CYREG_SCB2_I2C_S_CMD 0x4026006cu
#define CYREG_SCB2_I2C_CFG 0x40260070u
#define CYREG_SCB2_TX_CTRL 0x40260200u
#define CYREG_SCB2_TX_FIFO_CTRL 0x40260204u
#define CYREG_SCB2_TX_FIFO_STATUS 0x40260208u
#define CYREG_SCB2_TX_FIFO_WR 0x40260240u
#define CYREG_SCB2_RX_CTRL 0x40260300u
#define CYREG_SCB2_RX_FIFO_CTRL 0x40260304u
#define CYREG_SCB2_RX_FIFO_STATUS 0x40260308u
#define CYREG_SCB2_RX_MATCH 0x40260310u
#define CYREG_SCB2_RX_FIFO_RD 0x40260340u
#define CYREG_SCB2_RX_FIFO_RD_SILENT 0x40260344u
#define CYREG_SCB2_EZ_DATA0 0x40260400u
#define CYREG_SCB2_EZ_DATA1 0x40260404u
#define CYREG_SCB2_EZ_DATA2 0x40260408u
#define CYREG_SCB2_EZ_DATA3 0x4026040cu
#define CYREG_SCB2_EZ_DATA4 0x40260410u
#define CYREG_SCB2_EZ_DATA5 0x40260414u
#define CYREG_SCB2_EZ_DATA6 0x40260418u
#define CYREG_SCB2_EZ_DATA7 0x4026041cu
#define CYREG_SCB2_EZ_DATA8 0x40260420u
#define CYREG_SCB2_EZ_DATA9 0x40260424u
#define CYREG_SCB2_EZ_DATA10 0x40260428u
#define CYREG_SCB2_EZ_DATA11 0x4026042cu
#define CYREG_SCB2_EZ_DATA12 0x40260430u
#define CYREG_SCB2_EZ_DATA13 0x40260434u
#define CYREG_SCB2_EZ_DATA14 0x40260438u
#define CYREG_SCB2_EZ_DATA15 0x4026043cu
#define CYREG_SCB2_EZ_DATA16 0x40260440u
#define CYREG_SCB2_EZ_DATA17 0x40260444u
#define CYREG_SCB2_EZ_DATA18 0x40260448u
#define CYREG_SCB2_EZ_DATA19 0x4026044cu
#define CYREG_SCB2_EZ_DATA20 0x40260450u
#define CYREG_SCB2_EZ_DATA21 0x40260454u
#define CYREG_SCB2_EZ_DATA22 0x40260458u
#define CYREG_SCB2_EZ_DATA23 0x4026045cu
#define CYREG_SCB2_EZ_DATA24 0x40260460u
#define CYREG_SCB2_EZ_DATA25 0x40260464u
#define CYREG_SCB2_EZ_DATA26 0x40260468u
#define CYREG_SCB2_EZ_DATA27 0x4026046cu
#define CYREG_SCB2_EZ_DATA28 0x40260470u
#define CYREG_SCB2_EZ_DATA29 0x40260474u
#define CYREG_SCB2_EZ_DATA30 0x40260478u
#define CYREG_SCB2_EZ_DATA31 0x4026047cu
#define CYREG_SCB2_INTR_CAUSE 0x40260e00u
#define CYREG_SCB2_INTR_I2C_EC 0x40260e80u
#define CYREG_SCB2_INTR_I2C_EC_MASK 0x40260e88u
#define CYREG_SCB2_INTR_I2C_EC_MASKED 0x40260e8cu
#define CYREG_SCB2_INTR_SPI_EC 0x40260ec0u
#define CYREG_SCB2_INTR_SPI_EC_MASK 0x40260ec8u
#define CYREG_SCB2_INTR_SPI_EC_MASKED 0x40260eccu
#define CYREG_SCB2_INTR_M 0x40260f00u
#define CYREG_SCB2_INTR_M_SET 0x40260f04u
#define CYREG_SCB2_INTR_M_MASK 0x40260f08u
#define CYREG_SCB2_INTR_M_MASKED 0x40260f0cu
#define CYREG_SCB2_INTR_S 0x40260f40u
#define CYREG_SCB2_INTR_S_SET 0x40260f44u
#define CYREG_SCB2_INTR_S_MASK 0x40260f48u
#define CYREG_SCB2_INTR_S_MASKED 0x40260f4cu
#define CYREG_SCB2_INTR_TX 0x40260f80u
#define CYREG_SCB2_INTR_TX_SET 0x40260f84u
#define CYREG_SCB2_INTR_TX_MASK 0x40260f88u
#define CYREG_SCB2_INTR_TX_MASKED 0x40260f8cu
#define CYREG_SCB2_INTR_RX 0x40260fc0u
#define CYREG_SCB2_INTR_RX_SET 0x40260fc4u
#define CYREG_SCB2_INTR_RX_MASK 0x40260fc8u
#define CYREG_SCB2_INTR_RX_MASKED 0x40260fccu
#define CYDEV_SCB3_BASE 0x40270000u
#define CYDEV_SCB3_SIZE 0x00010000u
#define CYREG_SCB3_CTRL 0x40270000u
#define CYREG_SCB3_STATUS 0x40270004u
#define CYREG_SCB3_SPI_CTRL 0x40270020u
#define CYREG_SCB3_SPI_STATUS 0x40270024u
#define CYREG_SCB3_UART_CTRL 0x40270040u
#define CYREG_SCB3_UART_TX_CTRL 0x40270044u
#define CYREG_SCB3_UART_RX_CTRL 0x40270048u
#define CYREG_SCB3_UART_RX_STATUS 0x4027004cu
#define CYREG_SCB3_UART_FLOW_CTRL 0x40270050u
#define CYREG_SCB3_I2C_CTRL 0x40270060u
#define CYREG_SCB3_I2C_STATUS 0x40270064u
#define CYREG_SCB3_I2C_M_CMD 0x40270068u
#define CYREG_SCB3_I2C_S_CMD 0x4027006cu
#define CYREG_SCB3_I2C_CFG 0x40270070u
#define CYREG_SCB3_TX_CTRL 0x40270200u
#define CYREG_SCB3_TX_FIFO_CTRL 0x40270204u
#define CYREG_SCB3_TX_FIFO_STATUS 0x40270208u
#define CYREG_SCB3_TX_FIFO_WR 0x40270240u
#define CYREG_SCB3_RX_CTRL 0x40270300u
#define CYREG_SCB3_RX_FIFO_CTRL 0x40270304u
#define CYREG_SCB3_RX_FIFO_STATUS 0x40270308u
#define CYREG_SCB3_RX_MATCH 0x40270310u
#define CYREG_SCB3_RX_FIFO_RD 0x40270340u
#define CYREG_SCB3_RX_FIFO_RD_SILENT 0x40270344u
#define CYREG_SCB3_EZ_DATA0 0x40270400u
#define CYREG_SCB3_EZ_DATA1 0x40270404u
#define CYREG_SCB3_EZ_DATA2 0x40270408u
#define CYREG_SCB3_EZ_DATA3 0x4027040cu
#define CYREG_SCB3_EZ_DATA4 0x40270410u
#define CYREG_SCB3_EZ_DATA5 0x40270414u
#define CYREG_SCB3_EZ_DATA6 0x40270418u
#define CYREG_SCB3_EZ_DATA7 0x4027041cu
#define CYREG_SCB3_EZ_DATA8 0x40270420u
#define CYREG_SCB3_EZ_DATA9 0x40270424u
#define CYREG_SCB3_EZ_DATA10 0x40270428u
#define CYREG_SCB3_EZ_DATA11 0x4027042cu
#define CYREG_SCB3_EZ_DATA12 0x40270430u
#define CYREG_SCB3_EZ_DATA13 0x40270434u
#define CYREG_SCB3_EZ_DATA14 0x40270438u
#define CYREG_SCB3_EZ_DATA15 0x4027043cu
#define CYREG_SCB3_EZ_DATA16 0x40270440u
#define CYREG_SCB3_EZ_DATA17 0x40270444u
#define CYREG_SCB3_EZ_DATA18 0x40270448u
#define CYREG_SCB3_EZ_DATA19 0x4027044cu
#define CYREG_SCB3_EZ_DATA20 0x40270450u
#define CYREG_SCB3_EZ_DATA21 0x40270454u
#define CYREG_SCB3_EZ_DATA22 0x40270458u
#define CYREG_SCB3_EZ_DATA23 0x4027045cu
#define CYREG_SCB3_EZ_DATA24 0x40270460u
#define CYREG_SCB3_EZ_DATA25 0x40270464u
#define CYREG_SCB3_EZ_DATA26 0x40270468u
#define CYREG_SCB3_EZ_DATA27 0x4027046cu
#define CYREG_SCB3_EZ_DATA28 0x40270470u
#define CYREG_SCB3_EZ_DATA29 0x40270474u
#define CYREG_SCB3_EZ_DATA30 0x40270478u
#define CYREG_SCB3_EZ_DATA31 0x4027047cu
#define CYREG_SCB3_INTR_CAUSE 0x40270e00u
#define CYREG_SCB3_INTR_I2C_EC 0x40270e80u
#define CYREG_SCB3_INTR_I2C_EC_MASK 0x40270e88u
#define CYREG_SCB3_INTR_I2C_EC_MASKED 0x40270e8cu
#define CYREG_SCB3_INTR_SPI_EC 0x40270ec0u
#define CYREG_SCB3_INTR_SPI_EC_MASK 0x40270ec8u
#define CYREG_SCB3_INTR_SPI_EC_MASKED 0x40270eccu
#define CYREG_SCB3_INTR_M 0x40270f00u
#define CYREG_SCB3_INTR_M_SET 0x40270f04u
#define CYREG_SCB3_INTR_M_MASK 0x40270f08u
#define CYREG_SCB3_INTR_M_MASKED 0x40270f0cu
#define CYREG_SCB3_INTR_S 0x40270f40u
#define CYREG_SCB3_INTR_S_SET 0x40270f44u
#define CYREG_SCB3_INTR_S_MASK 0x40270f48u
#define CYREG_SCB3_INTR_S_MASKED 0x40270f4cu
#define CYREG_SCB3_INTR_TX 0x40270f80u
#define CYREG_SCB3_INTR_TX_SET 0x40270f84u
#define CYREG_SCB3_INTR_TX_MASK 0x40270f88u
#define CYREG_SCB3_INTR_TX_MASKED 0x40270f8cu
#define CYREG_SCB3_INTR_RX 0x40270fc0u
#define CYREG_SCB3_INTR_RX_SET 0x40270fc4u
#define CYREG_SCB3_INTR_RX_MASK 0x40270fc8u
#define CYREG_SCB3_INTR_RX_MASKED 0x40270fccu
#define CYDEV_SCB4_BASE 0x40280000u
#define CYDEV_SCB4_SIZE 0x00010000u
#define CYREG_SCB4_CTRL 0x40280000u
#define CYREG_SCB4_STATUS 0x40280004u
#define CYREG_SCB4_SPI_CTRL 0x40280020u
#define CYREG_SCB4_SPI_STATUS 0x40280024u
#define CYREG_SCB4_UART_CTRL 0x40280040u
#define CYREG_SCB4_UART_TX_CTRL 0x40280044u
#define CYREG_SCB4_UART_RX_CTRL 0x40280048u
#define CYREG_SCB4_UART_RX_STATUS 0x4028004cu
#define CYREG_SCB4_UART_FLOW_CTRL 0x40280050u
#define CYREG_SCB4_I2C_CTRL 0x40280060u
#define CYREG_SCB4_I2C_STATUS 0x40280064u
#define CYREG_SCB4_I2C_M_CMD 0x40280068u
#define CYREG_SCB4_I2C_S_CMD 0x4028006cu
#define CYREG_SCB4_I2C_CFG 0x40280070u
#define CYREG_SCB4_TX_CTRL 0x40280200u
#define CYREG_SCB4_TX_FIFO_CTRL 0x40280204u
#define CYREG_SCB4_TX_FIFO_STATUS 0x40280208u
#define CYREG_SCB4_TX_FIFO_WR 0x40280240u
#define CYREG_SCB4_RX_CTRL 0x40280300u
#define CYREG_SCB4_RX_FIFO_CTRL 0x40280304u
#define CYREG_SCB4_RX_FIFO_STATUS 0x40280308u
#define CYREG_SCB4_RX_MATCH 0x40280310u
#define CYREG_SCB4_RX_FIFO_RD 0x40280340u
#define CYREG_SCB4_RX_FIFO_RD_SILENT 0x40280344u
#define CYREG_SCB4_EZ_DATA0 0x40280400u
#define CYREG_SCB4_EZ_DATA1 0x40280404u
#define CYREG_SCB4_EZ_DATA2 0x40280408u
#define CYREG_SCB4_EZ_DATA3 0x4028040cu
#define CYREG_SCB4_EZ_DATA4 0x40280410u
#define CYREG_SCB4_EZ_DATA5 0x40280414u
#define CYREG_SCB4_EZ_DATA6 0x40280418u
#define CYREG_SCB4_EZ_DATA7 0x4028041cu
#define CYREG_SCB4_EZ_DATA8 0x40280420u
#define CYREG_SCB4_EZ_DATA9 0x40280424u
#define CYREG_SCB4_EZ_DATA10 0x40280428u
#define CYREG_SCB4_EZ_DATA11 0x4028042cu
#define CYREG_SCB4_EZ_DATA12 0x40280430u
#define CYREG_SCB4_EZ_DATA13 0x40280434u
#define CYREG_SCB4_EZ_DATA14 0x40280438u
#define CYREG_SCB4_EZ_DATA15 0x4028043cu
#define CYREG_SCB4_EZ_DATA16 0x40280440u
#define CYREG_SCB4_EZ_DATA17 0x40280444u
#define CYREG_SCB4_EZ_DATA18 0x40280448u
#define CYREG_SCB4_EZ_DATA19 0x4028044cu
#define CYREG_SCB4_EZ_DATA20 0x40280450u
#define CYREG_SCB4_EZ_DATA21 0x40280454u
#define CYREG_SCB4_EZ_DATA22 0x40280458u
#define CYREG_SCB4_EZ_DATA23 0x4028045cu
#define CYREG_SCB4_EZ_DATA24 0x40280460u
#define CYREG_SCB4_EZ_DATA25 0x40280464u
#define CYREG_SCB4_EZ_DATA26 0x40280468u
#define CYREG_SCB4_EZ_DATA27 0x4028046cu
#define CYREG_SCB4_EZ_DATA28 0x40280470u
#define CYREG_SCB4_EZ_DATA29 0x40280474u
#define CYREG_SCB4_EZ_DATA30 0x40280478u
#define CYREG_SCB4_EZ_DATA31 0x4028047cu
#define CYREG_SCB4_INTR_CAUSE 0x40280e00u
#define CYREG_SCB4_INTR_I2C_EC 0x40280e80u
#define CYREG_SCB4_INTR_I2C_EC_MASK 0x40280e88u
#define CYREG_SCB4_INTR_I2C_EC_MASKED 0x40280e8cu
#define CYREG_SCB4_INTR_SPI_EC 0x40280ec0u
#define CYREG_SCB4_INTR_SPI_EC_MASK 0x40280ec8u
#define CYREG_SCB4_INTR_SPI_EC_MASKED 0x40280eccu
#define CYREG_SCB4_INTR_M 0x40280f00u
#define CYREG_SCB4_INTR_M_SET 0x40280f04u
#define CYREG_SCB4_INTR_M_MASK 0x40280f08u
#define CYREG_SCB4_INTR_M_MASKED 0x40280f0cu
#define CYREG_SCB4_INTR_S 0x40280f40u
#define CYREG_SCB4_INTR_S_SET 0x40280f44u
#define CYREG_SCB4_INTR_S_MASK 0x40280f48u
#define CYREG_SCB4_INTR_S_MASKED 0x40280f4cu
#define CYREG_SCB4_INTR_TX 0x40280f80u
#define CYREG_SCB4_INTR_TX_SET 0x40280f84u
#define CYREG_SCB4_INTR_TX_MASK 0x40280f88u
#define CYREG_SCB4_INTR_TX_MASKED 0x40280f8cu
#define CYREG_SCB4_INTR_RX 0x40280fc0u
#define CYREG_SCB4_INTR_RX_SET 0x40280fc4u
#define CYREG_SCB4_INTR_RX_MASK 0x40280fc8u
#define CYREG_SCB4_INTR_RX_MASKED 0x40280fccu
#define CYDEV_CSD_BASE 0x40290000u
#define CYDEV_CSD_SIZE 0x00001000u
#define CYREG_CSD_CONFIG 0x40290000u
#define CYFLD_CSD_LOW_VDDA__OFFSET 0x00000003u
#define CYFLD_CSD_LOW_VDDA__SIZE 0x00000001u
#define CYFLD_CSD_FILTER_DELAY__OFFSET 0x00000004u
#define CYFLD_CSD_FILTER_DELAY__SIZE 0x00000003u
#define CYFLD_CSD_SHIELD_DELAY__OFFSET 0x00000008u
#define CYFLD_CSD_SHIELD_DELAY__SIZE 0x00000002u
#define CYVAL_CSD_SHIELD_DELAY_OFF 0x00000000u
#define CYVAL_CSD_SHIELD_DELAY_D5NS 0x00000001u
#define CYVAL_CSD_SHIELD_DELAY_D10NS 0x00000002u
#define CYVAL_CSD_SHIELD_DELAY_D20NS 0x00000003u
#define CYFLD_CSD_SENSE_EN__OFFSET 0x0000000cu
#define CYFLD_CSD_SENSE_EN__SIZE 0x00000001u
#define CYFLD_CSD_CHARGE_MODE__OFFSET 0x0000000eu
#define CYFLD_CSD_CHARGE_MODE__SIZE 0x00000001u
#define CYVAL_CSD_CHARGE_MODE_CHARGE_OFF 0x00000000u
#define CYVAL_CSD_CHARGE_MODE_CHARGE_IO 0x00000001u
#define CYFLD_CSD_FULL_WAVE__OFFSET 0x00000011u
#define CYFLD_CSD_FULL_WAVE__SIZE 0x00000001u
#define CYVAL_CSD_FULL_WAVE_HALFWAVE 0x00000000u
#define CYVAL_CSD_FULL_WAVE_FULLWAVE 0x00000001u
#define CYFLD_CSD_MUTUAL_CAP__OFFSET 0x00000012u
#define CYFLD_CSD_MUTUAL_CAP__SIZE 0x00000001u
#define CYVAL_CSD_MUTUAL_CAP_SELFCAP 0x00000000u
#define CYVAL_CSD_MUTUAL_CAP_MUTUALCAP 0x00000001u
#define CYFLD_CSD_CSX_DUAL_CNT__OFFSET 0x00000013u
#define CYFLD_CSD_CSX_DUAL_CNT__SIZE 0x00000001u
#define CYVAL_CSD_CSX_DUAL_CNT_ONE 0x00000000u
#define CYVAL_CSD_CSX_DUAL_CNT_TWO 0x00000001u
#define CYFLD_CSD_DSI_COUNT_SEL__OFFSET 0x00000018u
#define CYFLD_CSD_DSI_COUNT_SEL__SIZE 0x00000001u
#define CYVAL_CSD_DSI_COUNT_SEL_CSD_RESULT 0x00000000u
#define CYVAL_CSD_DSI_COUNT_SEL_ADC_RESULT 0x00000001u
#define CYFLD_CSD_DSI_SAMPLE_EN__OFFSET 0x00000019u
#define CYFLD_CSD_DSI_SAMPLE_EN__SIZE 0x00000001u
#define CYFLD_CSD_SAMPLE_SYNC__OFFSET 0x0000001au
#define CYFLD_CSD_SAMPLE_SYNC__SIZE 0x00000001u
#define CYFLD_CSD_DSI_SENSE_EN__OFFSET 0x0000001bu
#define CYFLD_CSD_DSI_SENSE_EN__SIZE 0x00000001u
#define CYFLD_CSD_LP_MODE__OFFSET 0x0000001eu
#define CYFLD_CSD_LP_MODE__SIZE 0x00000001u
#define CYFLD_CSD_ENABLE__OFFSET 0x0000001fu
#define CYFLD_CSD_ENABLE__SIZE 0x00000001u
#define CYREG_CSD_SPARE 0x40290004u
#define CYFLD_CSD_SPARE__OFFSET 0x00000000u
#define CYFLD_CSD_SPARE__SIZE 0x00000004u
#define CYREG_CSD_STATUS 0x40290080u
#define CYFLD_CSD_CSD_CHARGE__OFFSET 0x00000000u
#define CYFLD_CSD_CSD_CHARGE__SIZE 0x00000001u
#define CYFLD_CSD_CSD_SENSE__OFFSET 0x00000001u
#define CYFLD_CSD_CSD_SENSE__SIZE 0x00000001u
#define CYFLD_CSD_HSCMP_OUT__OFFSET 0x00000002u
#define CYFLD_CSD_HSCMP_OUT__SIZE 0x00000001u
#define CYVAL_CSD_HSCMP_OUT_C_LT_VREF 0x00000000u
#define CYVAL_CSD_HSCMP_OUT_C_GT_VREF 0x00000001u
#define CYFLD_CSD_CSDCMP_OUT__OFFSET 0x00000003u
#define CYFLD_CSD_CSDCMP_OUT__SIZE 0x00000001u
#define CYREG_CSD_STAT_SEQ 0x40290084u
#define CYFLD_CSD_SEQ_STATE__OFFSET 0x00000000u
#define CYFLD_CSD_SEQ_STATE__SIZE 0x00000003u
#define CYFLD_CSD_ADC_STATE__OFFSET 0x00000010u
#define CYFLD_CSD_ADC_STATE__SIZE 0x00000003u
#define CYREG_CSD_STAT_CNTS 0x40290088u
#define CYFLD_CSD_NUM_CONV__OFFSET 0x00000000u
#define CYFLD_CSD_NUM_CONV__SIZE 0x00000010u
#define CYREG_CSD_STAT_HCNT 0x4029008cu
#define CYFLD_CSD_CNT__OFFSET 0x00000000u
#define CYFLD_CSD_CNT__SIZE 0x00000010u
#define CYREG_CSD_RESULT_VAL1 0x402900d0u
#define CYFLD_CSD_VALUE__OFFSET 0x00000000u
#define CYFLD_CSD_VALUE__SIZE 0x00000010u
#define CYFLD_CSD_BAD_CONVS__OFFSET 0x00000010u
#define CYFLD_CSD_BAD_CONVS__SIZE 0x00000008u
#define CYREG_CSD_RESULT_VAL2 0x402900d4u
#define CYREG_CSD_ADC_RES 0x402900e0u
#define CYFLD_CSD_VIN_CNT__OFFSET 0x00000000u
#define CYFLD_CSD_VIN_CNT__SIZE 0x00000010u
#define CYFLD_CSD_HSCMP_POL__OFFSET 0x00000010u
#define CYFLD_CSD_HSCMP_POL__SIZE 0x00000001u
#define CYFLD_CSD_ADC_OVERFLOW__OFFSET 0x0000001eu
#define CYFLD_CSD_ADC_OVERFLOW__SIZE 0x00000001u
#define CYFLD_CSD_ADC_ABORT__OFFSET 0x0000001fu
#define CYFLD_CSD_ADC_ABORT__SIZE 0x00000001u
#define CYREG_CSD_INTR 0x402900f0u
#define CYFLD_CSD_SAMPLE__OFFSET 0x00000001u
#define CYFLD_CSD_SAMPLE__SIZE 0x00000001u
#define CYFLD_CSD_INIT__OFFSET 0x00000002u
#define CYFLD_CSD_INIT__SIZE 0x00000001u
#define CYFLD_CSD_ADC_RES__OFFSET 0x00000008u
#define CYFLD_CSD_ADC_RES__SIZE 0x00000001u
#define CYREG_CSD_INTR_SET 0x402900f4u
#define CYREG_CSD_INTR_MASK 0x402900f8u
#define CYREG_CSD_INTR_MASKED 0x402900fcu
#define CYREG_CSD_HSCMP 0x40290180u
#define CYFLD_CSD_HSCMP_EN__OFFSET 0x00000000u
#define CYFLD_CSD_HSCMP_EN__SIZE 0x00000001u
#define CYVAL_CSD_HSCMP_EN_OFF 0x00000000u
#define CYVAL_CSD_HSCMP_EN_ON 0x00000001u
#define CYFLD_CSD_HSCMP_INVERT__OFFSET 0x00000004u
#define CYFLD_CSD_HSCMP_INVERT__SIZE 0x00000001u
#define CYFLD_CSD_AZ_EN__OFFSET 0x0000001fu
#define CYFLD_CSD_AZ_EN__SIZE 0x00000001u
#define CYREG_CSD_AMBUF 0x40290184u
#define CYFLD_CSD_PWR_MODE__OFFSET 0x00000000u
#define CYFLD_CSD_PWR_MODE__SIZE 0x00000002u
#define CYVAL_CSD_PWR_MODE_OFF 0x00000000u
#define CYVAL_CSD_PWR_MODE_NORM 0x00000001u
#define CYVAL_CSD_PWR_MODE_HI 0x00000002u
#define CYREG_CSD_REFGEN 0x40290188u
#define CYFLD_CSD_REFGEN_EN__OFFSET 0x00000000u
#define CYFLD_CSD_REFGEN_EN__SIZE 0x00000001u
#define CYVAL_CSD_REFGEN_EN_OFF 0x00000000u
#define CYVAL_CSD_REFGEN_EN_ON 0x00000001u
#define CYFLD_CSD_BYPASS__OFFSET 0x00000004u
#define CYFLD_CSD_BYPASS__SIZE 0x00000001u
#define CYFLD_CSD_VDDA_EN__OFFSET 0x00000005u
#define CYFLD_CSD_VDDA_EN__SIZE 0x00000001u
#define CYFLD_CSD_RES_EN__OFFSET 0x00000006u
#define CYFLD_CSD_RES_EN__SIZE 0x00000001u
#define CYFLD_CSD_GAIN__OFFSET 0x00000008u
#define CYFLD_CSD_GAIN__SIZE 0x00000005u
#define CYFLD_CSD_VREFLO_SEL__OFFSET 0x00000010u
#define CYFLD_CSD_VREFLO_SEL__SIZE 0x00000005u
#define CYFLD_CSD_VREFLO_INT__OFFSET 0x00000017u
#define CYFLD_CSD_VREFLO_INT__SIZE 0x00000001u
#define CYREG_CSD_CSDCMP 0x4029018cu
#define CYFLD_CSD_CSDCMP_EN__OFFSET 0x00000000u
#define CYFLD_CSD_CSDCMP_EN__SIZE 0x00000001u
#define CYVAL_CSD_CSDCMP_EN_OFF 0x00000000u
#define CYVAL_CSD_CSDCMP_EN_ON 0x00000001u
#define CYFLD_CSD_POLARITY_SEL__OFFSET 0x00000004u
#define CYFLD_CSD_POLARITY_SEL__SIZE 0x00000002u
#define CYVAL_CSD_POLARITY_SEL_IDACA_POL 0x00000000u
#define CYVAL_CSD_POLARITY_SEL_IDACB_POL 0x00000001u
#define CYVAL_CSD_POLARITY_SEL_DUAL_POL 0x00000002u
#define CYFLD_CSD_CMP_PHASE__OFFSET 0x00000008u
#define CYFLD_CSD_CMP_PHASE__SIZE 0x00000002u
#define CYVAL_CSD_CMP_PHASE_FULL 0x00000000u
#define CYVAL_CSD_CMP_PHASE_PHI1 0x00000001u
#define CYVAL_CSD_CMP_PHASE_PHI2 0x00000002u
#define CYVAL_CSD_CMP_PHASE_PHI1_2 0x00000003u
#define CYFLD_CSD_CMP_MODE__OFFSET 0x0000001cu
#define CYFLD_CSD_CMP_MODE__SIZE 0x00000001u
#define CYVAL_CSD_CMP_MODE_CSD 0x00000000u
#define CYVAL_CSD_CMP_MODE_GP 0x00000001u
#define CYFLD_CSD_FEEDBACK_MODE__OFFSET 0x0000001du
#define CYFLD_CSD_FEEDBACK_MODE__SIZE 0x00000001u
#define CYVAL_CSD_FEEDBACK_MODE_FLOP 0x00000000u
#define CYVAL_CSD_FEEDBACK_MODE_COMP 0x00000001u
#define CYREG_CSD_IDACA 0x402901c0u
#define CYFLD_CSD_VAL__OFFSET 0x00000000u
#define CYFLD_CSD_VAL__SIZE 0x00000007u
#define CYFLD_CSD_POL_DYN__OFFSET 0x00000007u
#define CYFLD_CSD_POL_DYN__SIZE 0x00000001u
#define CYVAL_CSD_POL_DYN_STATIC 0x00000000u
#define CYVAL_CSD_POL_DYN_DYNAMIC 0x00000001u
#define CYFLD_CSD_POLARITY__OFFSET 0x00000008u
#define CYFLD_CSD_POLARITY__SIZE 0x00000002u
#define CYVAL_CSD_POLARITY_VSSA_SRC 0x00000000u
#define CYVAL_CSD_POLARITY_VDDA_SNK 0x00000001u
#define CYVAL_CSD_POLARITY_SENSE 0x00000002u
#define CYVAL_CSD_POLARITY_SENSE_INV 0x00000003u
#define CYFLD_CSD_BAL_MODE__OFFSET 0x0000000au
#define CYFLD_CSD_BAL_MODE__SIZE 0x00000002u
#define CYVAL_CSD_BAL_MODE_FULL 0x00000000u
#define CYVAL_CSD_BAL_MODE_PHI1 0x00000001u
#define CYVAL_CSD_BAL_MODE_PHI2 0x00000002u
#define CYVAL_CSD_BAL_MODE_PHI1_2 0x00000003u
#define CYFLD_CSD_LEG1_MODE__OFFSET 0x00000010u
#define CYFLD_CSD_LEG1_MODE__SIZE 0x00000002u
#define CYVAL_CSD_LEG1_MODE_GP_STATIC 0x00000000u
#define CYVAL_CSD_LEG1_MODE_GP 0x00000001u
#define CYVAL_CSD_LEG1_MODE_CSD_STATIC 0x00000002u
#define CYVAL_CSD_LEG1_MODE_CSD 0x00000003u
#define CYFLD_CSD_LEG2_MODE__OFFSET 0x00000012u
#define CYFLD_CSD_LEG2_MODE__SIZE 0x00000002u
#define CYVAL_CSD_LEG2_MODE_GP_STATIC 0x00000000u
#define CYVAL_CSD_LEG2_MODE_GP 0x00000001u
#define CYVAL_CSD_LEG2_MODE_CSD_STATIC 0x00000002u
#define CYVAL_CSD_LEG2_MODE_CSD 0x00000003u
#define CYFLD_CSD_DSI_CTRL_EN__OFFSET 0x00000015u
#define CYFLD_CSD_DSI_CTRL_EN__SIZE 0x00000001u
#define CYFLD_CSD_RANGE__OFFSET 0x00000016u
#define CYFLD_CSD_RANGE__SIZE 0x00000002u
#define CYVAL_CSD_RANGE_IDAC_LO 0x00000000u
#define CYVAL_CSD_RANGE_IDAC_MED 0x00000001u
#define CYVAL_CSD_RANGE_IDAC_HI 0x00000002u
#define CYVAL_CSD_RANGE_IDAC_MED2 0x00000003u
#define CYFLD_CSD_LEG1_EN__OFFSET 0x00000018u
#define CYFLD_CSD_LEG1_EN__SIZE 0x00000001u
#define CYFLD_CSD_LEG2_EN__OFFSET 0x00000019u
#define CYFLD_CSD_LEG2_EN__SIZE 0x00000001u
#define CYREG_CSD_IDACB 0x402901c4u
#define CYFLD_CSD_LEG3_EN__OFFSET 0x0000001au
#define CYFLD_CSD_LEG3_EN__SIZE 0x00000001u
#define CYREG_CSD_SW_RES 0x402901f0u
#define CYFLD_CSD_RES_HCAV__OFFSET 0x00000000u
#define CYFLD_CSD_RES_HCAV__SIZE 0x00000002u
#define CYVAL_CSD_RES_HCAV_LOW 0x00000000u
#define CYVAL_CSD_RES_HCAV_MED 0x00000001u
#define CYVAL_CSD_RES_HCAV_HIGH 0x00000002u
#define CYVAL_CSD_RES_HCAV_LOWEMI 0x00000003u
#define CYFLD_CSD_RES_HCAG__OFFSET 0x00000002u
#define CYFLD_CSD_RES_HCAG__SIZE 0x00000002u
#define CYFLD_CSD_RES_HCBV__OFFSET 0x00000004u
#define CYFLD_CSD_RES_HCBV__SIZE 0x00000002u
#define CYFLD_CSD_RES_HCBG__OFFSET 0x00000006u
#define CYFLD_CSD_RES_HCBG__SIZE 0x00000002u
#define CYFLD_CSD_RES_F1PM__OFFSET 0x00000010u
#define CYFLD_CSD_RES_F1PM__SIZE 0x00000002u
#define CYVAL_CSD_RES_F1PM_LOW 0x00000000u
#define CYVAL_CSD_RES_F1PM_MED 0x00000001u
#define CYVAL_CSD_RES_F1PM_HIGH 0x00000002u
#define CYVAL_CSD_RES_F1PM_RESERVED 0x00000003u
#define CYFLD_CSD_RES_F2PT__OFFSET 0x00000012u
#define CYFLD_CSD_RES_F2PT__SIZE 0x00000002u
#define CYREG_CSD_SENSE_PERIOD 0x40290200u
#define CYFLD_CSD_SENSE_DIV__OFFSET 0x00000000u
#define CYFLD_CSD_SENSE_DIV__SIZE 0x0000000cu
#define CYFLD_CSD_LFSR_SIZE__OFFSET 0x00000010u
#define CYFLD_CSD_LFSR_SIZE__SIZE 0x00000003u
#define CYVAL_CSD_LFSR_SIZE_OFF 0x00000000u
#define CYVAL_CSD_LFSR_SIZE_6B 0x00000001u
#define CYVAL_CSD_LFSR_SIZE_7B 0x00000002u
#define CYVAL_CSD_LFSR_SIZE_9B 0x00000003u
#define CYVAL_CSD_LFSR_SIZE_10B 0x00000004u
#define CYVAL_CSD_LFSR_SIZE_8B 0x00000005u
#define CYVAL_CSD_LFSR_SIZE_12B 0x00000006u
#define CYFLD_CSD_LFSR_SCALE__OFFSET 0x00000014u
#define CYFLD_CSD_LFSR_SCALE__SIZE 0x00000004u
#define CYFLD_CSD_LFSR_CLEAR__OFFSET 0x00000018u
#define CYFLD_CSD_LFSR_CLEAR__SIZE 0x00000001u
#define CYFLD_CSD_SEL_LFSR_MSB__OFFSET 0x00000019u
#define CYFLD_CSD_SEL_LFSR_MSB__SIZE 0x00000001u
#define CYFLD_CSD_LFSR_BITS__OFFSET 0x0000001au
#define CYFLD_CSD_LFSR_BITS__SIZE 0x00000002u
#define CYVAL_CSD_LFSR_BITS_2B 0x00000000u
#define CYVAL_CSD_LFSR_BITS_3B 0x00000001u
#define CYVAL_CSD_LFSR_BITS_4B 0x00000002u
#define CYVAL_CSD_LFSR_BITS_5B 0x00000003u
#define CYREG_CSD_SENSE_DUTY 0x40290204u
#define CYFLD_CSD_SENSE_WIDTH__OFFSET 0x00000000u
#define CYFLD_CSD_SENSE_WIDTH__SIZE 0x0000000cu
#define CYFLD_CSD_SENSE_POL__OFFSET 0x00000010u
#define CYFLD_CSD_SENSE_POL__SIZE 0x00000001u
#define CYFLD_CSD_OVERLAP_PHI1__OFFSET 0x00000012u
#define CYFLD_CSD_OVERLAP_PHI1__SIZE 0x00000001u
#define CYFLD_CSD_OVERLAP_PHI2__OFFSET 0x00000013u
#define CYFLD_CSD_OVERLAP_PHI2__SIZE 0x00000001u
#define CYREG_CSD_SW_HS_P_SEL 0x40290280u
#define CYFLD_CSD_SW_HMPM__OFFSET 0x00000000u
#define CYFLD_CSD_SW_HMPM__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMPT__OFFSET 0x00000004u
#define CYFLD_CSD_SW_HMPT__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMPS__OFFSET 0x00000008u
#define CYFLD_CSD_SW_HMPS__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMMA__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_HMMA__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMMB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_HMMB__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMCA__OFFSET 0x00000014u
#define CYFLD_CSD_SW_HMCA__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMCB__OFFSET 0x00000018u
#define CYFLD_CSD_SW_HMCB__SIZE 0x00000001u
#define CYFLD_CSD_SW_HMRH__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_HMRH__SIZE 0x00000001u
#define CYREG_CSD_SW_HS_N_SEL 0x40290284u
#define CYFLD_CSD_SW_HCCC__OFFSET 0x00000010u
#define CYFLD_CSD_SW_HCCC__SIZE 0x00000001u
#define CYFLD_CSD_SW_HCCD__OFFSET 0x00000014u
#define CYFLD_CSD_SW_HCCD__SIZE 0x00000001u
#define CYFLD_CSD_SW_HCRH__OFFSET 0x00000018u
#define CYFLD_CSD_SW_HCRH__SIZE 0x00000003u
#define CYFLD_CSD_SW_HCRL__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_HCRL__SIZE 0x00000003u
#define CYREG_CSD_SW_SHIELD_SEL 0x40290288u
#define CYFLD_CSD_SW_HCAV__OFFSET 0x00000000u
#define CYFLD_CSD_SW_HCAV__SIZE 0x00000003u
#define CYFLD_CSD_SW_HCAG__OFFSET 0x00000004u
#define CYFLD_CSD_SW_HCAG__SIZE 0x00000003u
#define CYFLD_CSD_SW_HCBV__OFFSET 0x00000008u
#define CYFLD_CSD_SW_HCBV__SIZE 0x00000003u
#define CYFLD_CSD_SW_HCBG__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_HCBG__SIZE 0x00000003u
#define CYFLD_CSD_SW_HCCV__OFFSET 0x00000010u
#define CYFLD_CSD_SW_HCCV__SIZE 0x00000001u
#define CYFLD_CSD_SW_HCCG__OFFSET 0x00000014u
#define CYFLD_CSD_SW_HCCG__SIZE 0x00000001u
#define CYREG_CSD_SW_HS_P_SEL1 0x4029028cu
#define CYFLD_CSD_SW_HMRE__OFFSET 0x00000000u
#define CYFLD_CSD_SW_HMRE__SIZE 0x00000001u
#define CYREG_CSD_SW_AMUXBUF_SEL 0x40290290u
#define CYFLD_CSD_SW_IRBY__OFFSET 0x00000004u
#define CYFLD_CSD_SW_IRBY__SIZE 0x00000001u
#define CYFLD_CSD_SW_IRLB__OFFSET 0x00000008u
#define CYFLD_CSD_SW_IRLB__SIZE 0x00000001u
#define CYFLD_CSD_SW_ICA__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_ICA__SIZE 0x00000001u
#define CYFLD_CSD_SW_ICB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_ICB__SIZE 0x00000003u
#define CYFLD_CSD_SW_IRLI__OFFSET 0x00000014u
#define CYFLD_CSD_SW_IRLI__SIZE 0x00000001u
#define CYFLD_CSD_SW_IRH__OFFSET 0x00000018u
#define CYFLD_CSD_SW_IRH__SIZE 0x00000001u
#define CYFLD_CSD_SW_IRL__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_IRL__SIZE 0x00000001u
#define CYREG_CSD_SW_BYP_SEL 0x40290294u
#define CYFLD_CSD_SW_BYA__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_BYA__SIZE 0x00000001u
#define CYFLD_CSD_SW_BYB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_BYB__SIZE 0x00000001u
#define CYFLD_CSD_SW_CBCC__OFFSET 0x00000014u
#define CYFLD_CSD_SW_CBCC__SIZE 0x00000001u
#define CYREG_CSD_SW_CMP_P_SEL 0x402902a0u
#define CYFLD_CSD_SW_SFPM__OFFSET 0x00000000u
#define CYFLD_CSD_SW_SFPM__SIZE 0x00000003u
#define CYFLD_CSD_SW_SFPT__OFFSET 0x00000004u
#define CYFLD_CSD_SW_SFPT__SIZE 0x00000003u
#define CYFLD_CSD_SW_SFPS__OFFSET 0x00000008u
#define CYFLD_CSD_SW_SFPS__SIZE 0x00000003u
#define CYFLD_CSD_SW_SFMA__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_SFMA__SIZE 0x00000001u
#define CYFLD_CSD_SW_SFMB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_SFMB__SIZE 0x00000001u
#define CYFLD_CSD_SW_SFCA__OFFSET 0x00000014u
#define CYFLD_CSD_SW_SFCA__SIZE 0x00000001u
#define CYFLD_CSD_SW_SFCB__OFFSET 0x00000018u
#define CYFLD_CSD_SW_SFCB__SIZE 0x00000001u
#define CYREG_CSD_SW_CMP_N_SEL 0x402902a4u
#define CYFLD_CSD_SW_SCRH__OFFSET 0x00000018u
#define CYFLD_CSD_SW_SCRH__SIZE 0x00000003u
#define CYFLD_CSD_SW_SCRL__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_SCRL__SIZE 0x00000003u
#define CYREG_CSD_SW_REFGEN_SEL 0x402902a8u
#define CYFLD_CSD_SW_IAIB__OFFSET 0x00000000u
#define CYFLD_CSD_SW_IAIB__SIZE 0x00000001u
#define CYFLD_CSD_SW_IBCB__OFFSET 0x00000004u
#define CYFLD_CSD_SW_IBCB__SIZE 0x00000001u
#define CYFLD_CSD_SW_SGMB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_SGMB__SIZE 0x00000001u
#define CYFLD_CSD_SW_SGRE__OFFSET 0x00000018u
#define CYFLD_CSD_SW_SGRE__SIZE 0x00000001u
#define CYFLD_CSD_SW_SGR__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_SGR__SIZE 0x00000001u
#define CYREG_CSD_SW_FW_MOD_SEL 0x402902b0u
#define CYFLD_CSD_SW_F1PM__OFFSET 0x00000000u
#define CYFLD_CSD_SW_F1PM__SIZE 0x00000001u
#define CYFLD_CSD_SW_F1MA__OFFSET 0x00000008u
#define CYFLD_CSD_SW_F1MA__SIZE 0x00000003u
#define CYFLD_CSD_SW_F1CA__OFFSET 0x00000010u
#define CYFLD_CSD_SW_F1CA__SIZE 0x00000003u
#define CYFLD_CSD_SW_C1CC__OFFSET 0x00000014u
#define CYFLD_CSD_SW_C1CC__SIZE 0x00000001u
#define CYFLD_CSD_SW_C1CD__OFFSET 0x00000018u
#define CYFLD_CSD_SW_C1CD__SIZE 0x00000001u
#define CYFLD_CSD_SW_C1F1__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_C1F1__SIZE 0x00000001u
#define CYREG_CSD_SW_FW_TANK_SEL 0x402902b4u
#define CYFLD_CSD_SW_F2PT__OFFSET 0x00000004u
#define CYFLD_CSD_SW_F2PT__SIZE 0x00000001u
#define CYFLD_CSD_SW_F2MA__OFFSET 0x00000008u
#define CYFLD_CSD_SW_F2MA__SIZE 0x00000003u
#define CYFLD_CSD_SW_F2CA__OFFSET 0x0000000cu
#define CYFLD_CSD_SW_F2CA__SIZE 0x00000003u
#define CYFLD_CSD_SW_F2CB__OFFSET 0x00000010u
#define CYFLD_CSD_SW_F2CB__SIZE 0x00000003u
#define CYFLD_CSD_SW_C2CC__OFFSET 0x00000014u
#define CYFLD_CSD_SW_C2CC__SIZE 0x00000001u
#define CYFLD_CSD_SW_C2CD__OFFSET 0x00000018u
#define CYFLD_CSD_SW_C2CD__SIZE 0x00000001u
#define CYFLD_CSD_SW_C2F2__OFFSET 0x0000001cu
#define CYFLD_CSD_SW_C2F2__SIZE 0x00000001u
#define CYREG_CSD_SW_DSI_SEL 0x402902c0u
#define CYFLD_CSD_DSI_CSH_TANK__OFFSET 0x00000000u
#define CYFLD_CSD_DSI_CSH_TANK__SIZE 0x00000003u
#define CYFLD_CSD_DSI_CMOD__OFFSET 0x00000004u
#define CYFLD_CSD_DSI_CMOD__SIZE 0x00000003u
#define CYREG_CSD_SEQ_TIME 0x40290300u
#define CYFLD_CSD_AZ_TIME__OFFSET 0x00000000u
#define CYFLD_CSD_AZ_TIME__SIZE 0x00000008u
#define CYREG_CSD_SEQ_INIT_CNT 0x40290310u
#define CYFLD_CSD_CONV_CNT__OFFSET 0x00000000u
#define CYFLD_CSD_CONV_CNT__SIZE 0x00000010u
#define CYREG_CSD_SEQ_NORM_CNT 0x40290314u
#define CYREG_CSD_ADC_CTL 0x40290320u
#define CYFLD_CSD_ADC_TIME__OFFSET 0x00000000u
#define CYFLD_CSD_ADC_TIME__SIZE 0x00000008u
#define CYFLD_CSD_ADC_MODE__OFFSET 0x00000010u
#define CYFLD_CSD_ADC_MODE__SIZE 0x00000002u
#define CYVAL_CSD_ADC_MODE_OFF 0x00000000u
#define CYVAL_CSD_ADC_MODE_VREF_CNT 0x00000001u
#define CYVAL_CSD_ADC_MODE_VREF_BY2_CNT 0x00000002u
#define CYVAL_CSD_ADC_MODE_VIN_CNT 0x00000003u
#define CYREG_CSD_SEQ_START 0x40290340u
#define CYFLD_CSD_START__OFFSET 0x00000000u
#define CYFLD_CSD_START__SIZE 0x00000001u
#define CYFLD_CSD_SEQ_MODE__OFFSET 0x00000001u
#define CYFLD_CSD_SEQ_MODE__SIZE 0x00000001u
#define CYFLD_CSD_ABORT__OFFSET 0x00000003u
#define CYFLD_CSD_ABORT__SIZE 0x00000001u
#define CYFLD_CSD_DSI_START_EN__OFFSET 0x00000004u
#define CYFLD_CSD_DSI_START_EN__SIZE 0x00000001u
#define CYFLD_CSD_AZ0_SKIP__OFFSET 0x00000008u
#define CYFLD_CSD_AZ0_SKIP__SIZE 0x00000001u
#define CYFLD_CSD_AZ1_SKIP__OFFSET 0x00000009u
#define CYFLD_CSD_AZ1_SKIP__SIZE 0x00000001u
#define CYDEV_LCD_BASE 0x402a0000u
#define CYDEV_LCD_SIZE 0x00010000u
#define CYREG_LCD_ID 0x402a0000u
#define CYFLD_LCD_ID__OFFSET 0x00000000u
#define CYFLD_LCD_ID__SIZE 0x00000010u
#define CYFLD_LCD_REVISION__OFFSET 0x00000010u
#define CYFLD_LCD_REVISION__SIZE 0x00000010u
#define CYREG_LCD_DIVIDER 0x402a0004u
#define CYFLD_LCD_SUBFR_DIV__OFFSET 0x00000000u
#define CYFLD_LCD_SUBFR_DIV__SIZE 0x00000010u
#define CYFLD_LCD_DEAD_DIV__OFFSET 0x00000010u
#define CYFLD_LCD_DEAD_DIV__SIZE 0x00000010u
#define CYREG_LCD_CONTROL 0x402a0008u
#define CYFLD_LCD_LS_EN__OFFSET 0x00000000u
#define CYFLD_LCD_LS_EN__SIZE 0x00000001u
#define CYFLD_LCD_HS_EN__OFFSET 0x00000001u
#define CYFLD_LCD_HS_EN__SIZE 0x00000001u
#define CYFLD_LCD_LCD_MODE__OFFSET 0x00000002u
#define CYFLD_LCD_LCD_MODE__SIZE 0x00000001u
#define CYVAL_LCD_LCD_MODE_LS 0x00000000u
#define CYVAL_LCD_LCD_MODE_HS 0x00000001u
#define CYFLD_LCD_TYPE__OFFSET 0x00000003u
#define CYFLD_LCD_TYPE__SIZE 0x00000001u
#define CYVAL_LCD_TYPE_TYPE_A 0x00000000u
#define CYVAL_LCD_TYPE_TYPE_B 0x00000001u
#define CYFLD_LCD_OP_MODE__OFFSET 0x00000004u
#define CYFLD_LCD_OP_MODE__SIZE 0x00000001u
#define CYVAL_LCD_OP_MODE_PWM 0x00000000u
#define CYVAL_LCD_OP_MODE_CORRELATION 0x00000001u
#define CYFLD_LCD_BIAS__OFFSET 0x00000005u
#define CYFLD_LCD_BIAS__SIZE 0x00000002u
#define CYVAL_LCD_BIAS_HALF 0x00000000u
#define CYVAL_LCD_BIAS_THIRD 0x00000001u
#define CYVAL_LCD_BIAS_FOURTH 0x00000002u
#define CYVAL_LCD_BIAS_FIFTH 0x00000003u
#define CYFLD_LCD_COM_NUM__OFFSET 0x00000008u
#define CYFLD_LCD_COM_NUM__SIZE 0x00000004u
#define CYFLD_LCD_LS_EN_STAT__OFFSET 0x0000001fu
#define CYFLD_LCD_LS_EN_STAT__SIZE 0x00000001u
#define CYREG_LCD_DATA00 0x402a0100u
#define CYFLD_LCD_DATA__OFFSET 0x00000000u
#define CYFLD_LCD_DATA__SIZE 0x00000020u
#define CYREG_LCD_DATA01 0x402a0104u
#define CYREG_LCD_DATA02 0x402a0108u
#define CYREG_LCD_DATA03 0x402a010cu
#define CYREG_LCD_DATA04 0x402a0110u
#define CYREG_LCD_DATA05 0x402a0114u
#define CYREG_LCD_DATA06 0x402a0118u
#define CYREG_LCD_DATA07 0x402a011cu
#define CYREG_LCD_DATA10 0x402a0200u
#define CYREG_LCD_DATA11 0x402a0204u
#define CYREG_LCD_DATA12 0x402a0208u
#define CYREG_LCD_DATA13 0x402a020cu
#define CYREG_LCD_DATA14 0x402a0210u
#define CYREG_LCD_DATA15 0x402a0214u
#define CYREG_LCD_DATA16 0x402a0218u
#define CYREG_LCD_DATA17 0x402a021cu
#define CYDEV_LPCOMP_BASE 0x402b0000u
#define CYDEV_LPCOMP_SIZE 0x00010000u
#define CYREG_LPCOMP_ID 0x402b0000u
#define CYFLD_LPCOMP_ID__OFFSET 0x00000000u
#define CYFLD_LPCOMP_ID__SIZE 0x00000010u
#define CYFLD_LPCOMP_REVISION__OFFSET 0x00000010u
#define CYFLD_LPCOMP_REVISION__SIZE 0x00000010u
#define CYREG_LPCOMP_CONFIG 0x402b0004u
#define CYFLD_LPCOMP_MODE1__OFFSET 0x00000000u
#define CYFLD_LPCOMP_MODE1__SIZE 0x00000002u
#define CYVAL_LPCOMP_MODE1_SLOW 0x00000000u
#define CYVAL_LPCOMP_MODE1_FAST 0x00000001u
#define CYVAL_LPCOMP_MODE1_ULP 0x00000002u
#define CYFLD_LPCOMP_HYST1__OFFSET 0x00000002u
#define CYFLD_LPCOMP_HYST1__SIZE 0x00000001u
#define CYFLD_LPCOMP_FILTER1__OFFSET 0x00000003u
#define CYFLD_LPCOMP_FILTER1__SIZE 0x00000001u
#define CYFLD_LPCOMP_INTTYPE1__OFFSET 0x00000004u
#define CYFLD_LPCOMP_INTTYPE1__SIZE 0x00000002u
#define CYVAL_LPCOMP_INTTYPE1_DISABLE 0x00000000u
#define CYVAL_LPCOMP_INTTYPE1_RISING 0x00000001u
#define CYVAL_LPCOMP_INTTYPE1_FALLING 0x00000002u
#define CYVAL_LPCOMP_INTTYPE1_BOTH 0x00000003u
#define CYFLD_LPCOMP_OUT1__OFFSET 0x00000006u
#define CYFLD_LPCOMP_OUT1__SIZE 0x00000001u
#define CYFLD_LPCOMP_ENABLE1__OFFSET 0x00000007u
#define CYFLD_LPCOMP_ENABLE1__SIZE 0x00000001u
#define CYFLD_LPCOMP_MODE2__OFFSET 0x00000008u
#define CYFLD_LPCOMP_MODE2__SIZE 0x00000002u
#define CYVAL_LPCOMP_MODE2_SLOW 0x00000000u
#define CYVAL_LPCOMP_MODE2_FAST 0x00000001u
#define CYVAL_LPCOMP_MODE2_ULP 0x00000002u
#define CYFLD_LPCOMP_HYST2__OFFSET 0x0000000au
#define CYFLD_LPCOMP_HYST2__SIZE 0x00000001u
#define CYFLD_LPCOMP_FILTER2__OFFSET 0x0000000bu
#define CYFLD_LPCOMP_FILTER2__SIZE 0x00000001u
#define CYFLD_LPCOMP_INTTYPE2__OFFSET 0x0000000cu
#define CYFLD_LPCOMP_INTTYPE2__SIZE 0x00000002u
#define CYVAL_LPCOMP_INTTYPE2_DISABLE 0x00000000u
#define CYVAL_LPCOMP_INTTYPE2_RISING 0x00000001u
#define CYVAL_LPCOMP_INTTYPE2_FALLING 0x00000002u
#define CYVAL_LPCOMP_INTTYPE2_BOTH 0x00000003u
#define CYFLD_LPCOMP_OUT2__OFFSET 0x0000000eu
#define CYFLD_LPCOMP_OUT2__SIZE 0x00000001u
#define CYFLD_LPCOMP_ENABLE2__OFFSET 0x0000000fu
#define CYFLD_LPCOMP_ENABLE2__SIZE 0x00000001u
#define CYFLD_LPCOMP_DSI_BYPASS1__OFFSET 0x00000010u
#define CYFLD_LPCOMP_DSI_BYPASS1__SIZE 0x00000001u
#define CYFLD_LPCOMP_DSI_LEVEL1__OFFSET 0x00000011u
#define CYFLD_LPCOMP_DSI_LEVEL1__SIZE 0x00000001u
#define CYFLD_LPCOMP_DSI_BYPASS2__OFFSET 0x00000014u
#define CYFLD_LPCOMP_DSI_BYPASS2__SIZE 0x00000001u
#define CYFLD_LPCOMP_DSI_LEVEL2__OFFSET 0x00000015u
#define CYFLD_LPCOMP_DSI_LEVEL2__SIZE 0x00000001u
#define CYREG_LPCOMP_DFT 0x402b0008u
#define CYFLD_LPCOMP_CAL_EN__OFFSET 0x00000000u
#define CYFLD_LPCOMP_CAL_EN__SIZE 0x00000001u
#define CYFLD_LPCOMP_BYPASS__OFFSET 0x00000001u
#define CYFLD_LPCOMP_BYPASS__SIZE 0x00000001u
#define CYREG_LPCOMP_INTR 0x402b0010u
#define CYFLD_LPCOMP_COMP1__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1__SIZE 0x00000001u
#define CYFLD_LPCOMP_COMP2__OFFSET 0x00000001u
#define CYFLD_LPCOMP_COMP2__SIZE 0x00000001u
#define CYREG_LPCOMP_INTR_SET 0x402b0014u
#define CYREG_LPCOMP_INTR_MASK 0x402b0018u
#define CYFLD_LPCOMP_COMP1_MASK__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1_MASK__SIZE 0x00000001u
#define CYFLD_LPCOMP_COMP2_MASK__OFFSET 0x00000001u
#define CYFLD_LPCOMP_COMP2_MASK__SIZE 0x00000001u
#define CYREG_LPCOMP_INTR_MASKED 0x402b001cu
#define CYFLD_LPCOMP_COMP1_MASKED__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1_MASKED__SIZE 0x00000001u
#define CYFLD_LPCOMP_COMP2_MASKED__OFFSET 0x00000001u
#define CYFLD_LPCOMP_COMP2_MASKED__SIZE 0x00000001u
#define CYREG_LPCOMP_TRIM1 0x402bff00u
#define CYFLD_LPCOMP_COMP1_TRIMA__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1_TRIMA__SIZE 0x00000005u
#define CYREG_LPCOMP_TRIM2 0x402bff04u
#define CYFLD_LPCOMP_COMP1_TRIMB__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP1_TRIMB__SIZE 0x00000005u
#define CYREG_LPCOMP_TRIM3 0x402bff08u
#define CYFLD_LPCOMP_COMP2_TRIMA__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP2_TRIMA__SIZE 0x00000005u
#define CYREG_LPCOMP_TRIM4 0x402bff0cu
#define CYFLD_LPCOMP_COMP2_TRIMB__OFFSET 0x00000000u
#define CYFLD_LPCOMP_COMP2_TRIMB__SIZE 0x00000005u
#define CYDEV_CRYPTO_BASE 0x402c0000u
#define CYDEV_CRYPTO_SIZE 0x00010000u
#define CYREG_CRYPTO_CTL 0x402c0000u
#define CYFLD_CRYPTO_OPCODE__OFFSET 0x00000000u
#define CYFLD_CRYPTO_OPCODE__SIZE 0x00000005u
#define CYVAL_CRYPTO_OPCODE_AES_FORWARD 0x00000000u
#define CYVAL_CRYPTO_OPCODE_AES_INVERSE 0x00000001u
#define CYVAL_CRYPTO_OPCODE_SHA 0x00000010u
#define CYVAL_CRYPTO_OPCODE_CRC 0x00000018u
#define CYFLD_CRYPTO_ENABLED__OFFSET 0x0000001fu
#define CYFLD_CRYPTO_ENABLED__SIZE 0x00000001u
#define CYREG_CRYPTO_STATUS 0x402c0004u
#define CYFLD_CRYPTO_BUSY__OFFSET 0x00000000u
#define CYFLD_CRYPTO_BUSY__SIZE 0x00000001u
#define CYREG_CRYPTO_CMD 0x402c0008u
#define CYFLD_CRYPTO_START__OFFSET 0x00000000u
#define CYFLD_CRYPTO_START__SIZE 0x00000001u
#define CYREG_CRYPTO_TR_CTL0 0x402c0280u
#define CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__OFFSET 0x00000000u
#define CYFLD_CRYPTO_SAMPLE_CLOCK_DIV__SIZE 0x00000008u
#define CYFLD_CRYPTO_RED_CLOCK_DIV__OFFSET 0x00000008u
#define CYFLD_CRYPTO_RED_CLOCK_DIV__SIZE 0x00000008u
#define CYFLD_CRYPTO_INIT_DELAY__OFFSET 0x00000010u
#define CYFLD_CRYPTO_INIT_DELAY__SIZE 0x00000008u
#define CYFLD_CRYPTO_VON_NEUMANN_CORR__OFFSET 0x00000018u
#define CYFLD_CRYPTO_VON_NEUMANN_CORR__SIZE 0x00000001u
#define CYFLD_CRYPTO_STOP_ON_AP_DETECT__OFFSET 0x0000001cu
#define CYFLD_CRYPTO_STOP_ON_AP_DETECT__SIZE 0x00000001u
#define CYFLD_CRYPTO_STOP_ON_RC_DETECT__OFFSET 0x0000001du
#define CYFLD_CRYPTO_STOP_ON_RC_DETECT__SIZE 0x00000001u
#define CYREG_CRYPTO_TR_CTL1 0x402c0284u
#define CYFLD_CRYPTO_DATA_BIT_SIZE__OFFSET 0x00000000u
#define CYFLD_CRYPTO_DATA_BIT_SIZE__SIZE 0x00000006u
#define CYREG_CRYPTO_TR_RESULT0 0x402c0288u
#define CYFLD_CRYPTO_DATA32__OFFSET 0x00000000u
#define CYFLD_CRYPTO_DATA32__SIZE 0x00000020u
#define CYREG_CRYPTO_TR_RESULT1 0x402c028cu
#define CYREG_CRYPTO_TR_CMD 0x402c0290u
#define CYFLD_CRYPTO_START_RO11__OFFSET 0x00000000u
#define CYFLD_CRYPTO_START_RO11__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_RO15__OFFSET 0x00000001u
#define CYFLD_CRYPTO_START_RO15__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_GARO15__OFFSET 0x00000002u
#define CYFLD_CRYPTO_START_GARO15__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_GARO31__OFFSET 0x00000003u
#define CYFLD_CRYPTO_START_GARO31__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_FIRO15__OFFSET 0x00000004u
#define CYFLD_CRYPTO_START_FIRO15__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_FIRO31__OFFSET 0x00000005u
#define CYFLD_CRYPTO_START_FIRO31__SIZE 0x00000001u
#define CYREG_CRYPTO_TR_GARO_CTL 0x402c02a0u
#define CYFLD_CRYPTO_POLYNOMIAL31__OFFSET 0x00000000u
#define CYFLD_CRYPTO_POLYNOMIAL31__SIZE 0x0000001fu
#define CYREG_CRYPTO_TR_FIRO_CTL 0x402c02a4u
#define CYREG_CRYPTO_TR_MON_CTL 0x402c02c0u
#define CYFLD_CRYPTO_BITSTREAM_SEL__OFFSET 0x00000000u
#define CYFLD_CRYPTO_BITSTREAM_SEL__SIZE 0x00000002u
#define CYREG_CRYPTO_TR_MON_CMD 0x402c02c8u
#define CYFLD_CRYPTO_START_AP__OFFSET 0x00000000u
#define CYFLD_CRYPTO_START_AP__SIZE 0x00000001u
#define CYFLD_CRYPTO_START_RC__OFFSET 0x00000001u
#define CYFLD_CRYPTO_START_RC__SIZE 0x00000001u
#define CYREG_CRYPTO_TR_MON_RC_CTL 0x402c02d0u
#define CYFLD_CRYPTO_CUTOFF_COUNT8__OFFSET 0x00000000u
#define CYFLD_CRYPTO_CUTOFF_COUNT8__SIZE 0x00000008u
#define CYREG_CRYPTO_TR_MON_RC_STATUS0 0x402c02d8u
#define CYFLD_CRYPTO_BIT__OFFSET 0x00000000u
#define CYFLD_CRYPTO_BIT__SIZE 0x00000001u
#define CYREG_CRYPTO_TR_MON_RC_STATUS1 0x402c02dcu
#define CYFLD_CRYPTO_REP_COUNT__OFFSET 0x00000000u
#define CYFLD_CRYPTO_REP_COUNT__SIZE 0x00000008u
#define CYREG_CRYPTO_TR_MON_AP_CTL 0x402c02e0u
#define CYFLD_CRYPTO_CUTOFF_COUNT16__OFFSET 0x00000000u
#define CYFLD_CRYPTO_CUTOFF_COUNT16__SIZE 0x00000010u
#define CYFLD_CRYPTO_WINDOW_SIZE__OFFSET 0x00000010u
#define CYFLD_CRYPTO_WINDOW_SIZE__SIZE 0x00000010u
#define CYREG_CRYPTO_TR_MON_AP_STATUS0 0x402c02e8u
#define CYREG_CRYPTO_TR_MON_AP_STATUS1 0x402c02ecu
#define CYFLD_CRYPTO_OCC_COUNT__OFFSET 0x00000000u
#define CYFLD_CRYPTO_OCC_COUNT__SIZE 0x00000010u
#define CYFLD_CRYPTO_WINDOW_INDEX__OFFSET 0x00000010u
#define CYFLD_CRYPTO_WINDOW_INDEX__SIZE 0x00000010u
#define CYREG_CRYPTO_INTR 0x402c07c0u
#define CYFLD_CRYPTO_DONE__OFFSET 0x00000000u
#define CYFLD_CRYPTO_DONE__SIZE 0x00000001u
#define CYFLD_CRYPTO_ACCESS_ERROR__OFFSET 0x00000001u
#define CYFLD_CRYPTO_ACCESS_ERROR__SIZE 0x00000001u
#define CYFLD_CRYPTO_TR_INITIALIZED__OFFSET 0x00000006u
#define CYFLD_CRYPTO_TR_INITIALIZED__SIZE 0x00000001u
#define CYFLD_CRYPTO_TR_DATA_AVAILABLE__OFFSET 0x00000007u
#define CYFLD_CRYPTO_TR_DATA_AVAILABLE__SIZE 0x00000001u
#define CYFLD_CRYPTO_TR_AP_DETECT__OFFSET 0x00000008u
#define CYFLD_CRYPTO_TR_AP_DETECT__SIZE 0x00000001u
#define CYFLD_CRYPTO_TR_RC_DETECT__OFFSET 0x00000009u
#define CYFLD_CRYPTO_TR_RC_DETECT__SIZE 0x00000001u
#define CYREG_CRYPTO_INTR_SET 0x402c07c4u
#define CYREG_CRYPTO_INTR_MASK 0x402c07c8u
#define CYREG_CRYPTO_INTR_MASKED 0x402c07ccu
#define CYREG_CRYPTO_MEM_BUFF0 0x402c0800u
#define CYREG_CRYPTO_MEM_BUFF1 0x402c0804u
#define CYREG_CRYPTO_MEM_BUFF2 0x402c0808u
#define CYREG_CRYPTO_MEM_BUFF3 0x402c080cu
#define CYREG_CRYPTO_MEM_BUFF4 0x402c0810u
#define CYREG_CRYPTO_MEM_BUFF5 0x402c0814u
#define CYREG_CRYPTO_MEM_BUFF6 0x402c0818u
#define CYREG_CRYPTO_MEM_BUFF7 0x402c081cu
#define CYREG_CRYPTO_MEM_BUFF8 0x402c0820u
#define CYREG_CRYPTO_MEM_BUFF9 0x402c0824u
#define CYREG_CRYPTO_MEM_BUFF10 0x402c0828u
#define CYREG_CRYPTO_MEM_BUFF11 0x402c082cu
#define CYREG_CRYPTO_MEM_BUFF12 0x402c0830u
#define CYREG_CRYPTO_MEM_BUFF13 0x402c0834u
#define CYREG_CRYPTO_MEM_BUFF14 0x402c0838u
#define CYREG_CRYPTO_MEM_BUFF15 0x402c083cu
#define CYREG_CRYPTO_MEM_BUFF16 0x402c0840u
#define CYREG_CRYPTO_MEM_BUFF17 0x402c0844u
#define CYREG_CRYPTO_MEM_BUFF18 0x402c0848u
#define CYREG_CRYPTO_MEM_BUFF19 0x402c084cu
#define CYREG_CRYPTO_MEM_BUFF20 0x402c0850u
#define CYREG_CRYPTO_MEM_BUFF21 0x402c0854u
#define CYREG_CRYPTO_MEM_BUFF22 0x402c0858u
#define CYREG_CRYPTO_MEM_BUFF23 0x402c085cu
#define CYREG_CRYPTO_MEM_BUFF24 0x402c0860u
#define CYREG_CRYPTO_MEM_BUFF25 0x402c0864u
#define CYREG_CRYPTO_MEM_BUFF26 0x402c0868u
#define CYREG_CRYPTO_MEM_BUFF27 0x402c086cu
#define CYREG_CRYPTO_MEM_BUFF28 0x402c0870u
#define CYREG_CRYPTO_MEM_BUFF29 0x402c0874u
#define CYREG_CRYPTO_MEM_BUFF30 0x402c0878u
#define CYREG_CRYPTO_MEM_BUFF31 0x402c087cu
#define CYREG_CRYPTO_MEM_BUFF32 0x402c0880u
#define CYREG_CRYPTO_MEM_BUFF33 0x402c0884u
#define CYREG_CRYPTO_MEM_BUFF34 0x402c0888u
#define CYREG_CRYPTO_MEM_BUFF35 0x402c088cu
#define CYREG_CRYPTO_MEM_BUFF36 0x402c0890u
#define CYREG_CRYPTO_MEM_BUFF37 0x402c0894u
#define CYREG_CRYPTO_MEM_BUFF38 0x402c0898u
#define CYREG_CRYPTO_MEM_BUFF39 0x402c089cu
#define CYREG_CRYPTO_MEM_BUFF40 0x402c08a0u
#define CYREG_CRYPTO_MEM_BUFF41 0x402c08a4u
#define CYREG_CRYPTO_MEM_BUFF42 0x402c08a8u
#define CYREG_CRYPTO_MEM_BUFF43 0x402c08acu
#define CYREG_CRYPTO_MEM_BUFF44 0x402c08b0u
#define CYREG_CRYPTO_MEM_BUFF45 0x402c08b4u
#define CYREG_CRYPTO_MEM_BUFF46 0x402c08b8u
#define CYREG_CRYPTO_MEM_BUFF47 0x402c08bcu
#define CYREG_CRYPTO_MEM_BUFF48 0x402c08c0u
#define CYREG_CRYPTO_MEM_BUFF49 0x402c08c4u
#define CYREG_CRYPTO_MEM_BUFF50 0x402c08c8u
#define CYREG_CRYPTO_MEM_BUFF51 0x402c08ccu
#define CYREG_CRYPTO_MEM_BUFF52 0x402c08d0u
#define CYREG_CRYPTO_MEM_BUFF53 0x402c08d4u
#define CYREG_CRYPTO_MEM_BUFF54 0x402c08d8u
#define CYREG_CRYPTO_MEM_BUFF55 0x402c08dcu
#define CYREG_CRYPTO_MEM_BUFF56 0x402c08e0u
#define CYREG_CRYPTO_MEM_BUFF57 0x402c08e4u
#define CYREG_CRYPTO_MEM_BUFF58 0x402c08e8u
#define CYREG_CRYPTO_MEM_BUFF59 0x402c08ecu
#define CYREG_CRYPTO_MEM_BUFF60 0x402c08f0u
#define CYREG_CRYPTO_MEM_BUFF61 0x402c08f4u
#define CYREG_CRYPTO_MEM_BUFF62 0x402c08f8u
#define CYREG_CRYPTO_MEM_BUFF63 0x402c08fcu
#define CYREG_CRYPTO_PRIV_BUF 0x402cff00u
#define CYFLD_CRYPTO_BUF_PRIV_LIMIT__OFFSET 0x00000000u
#define CYFLD_CRYPTO_BUF_PRIV_LIMIT__SIZE 0x00000003u
#define CYDEV_CAN_BASE 0x402e0000u
#define CYDEV_CAN_SIZE 0x00010000u
#define CYREG_CAN_INT_STATUS 0x402e0000u
#define CYFLD_CAN_ARB_LOSS__OFFSET 0x00000002u
#define CYFLD_CAN_ARB_LOSS__SIZE 0x00000001u
#define CYFLD_CAN_OVR_LOAD__OFFSET 0x00000003u
#define CYFLD_CAN_OVR_LOAD__SIZE 0x00000001u
#define CYFLD_CAN_BIT_ERR__OFFSET 0x00000004u
#define CYFLD_CAN_BIT_ERR__SIZE 0x00000001u
#define CYFLD_CAN_STUFF_ERR__OFFSET 0x00000005u
#define CYFLD_CAN_STUFF_ERR__SIZE 0x00000001u
#define CYFLD_CAN_ACK_ERR__OFFSET 0x00000006u
#define CYFLD_CAN_ACK_ERR__SIZE 0x00000001u
#define CYFLD_CAN_FORM_ERR__OFFSET 0x00000007u
#define CYFLD_CAN_FORM_ERR__SIZE 0x00000001u
#define CYFLD_CAN_CRC_ERR__OFFSET 0x00000008u
#define CYFLD_CAN_CRC_ERR__SIZE 0x00000001u
#define CYFLD_CAN_BUS_OFF__OFFSET 0x00000009u
#define CYFLD_CAN_BUS_OFF__SIZE 0x00000001u
#define CYFLD_CAN_RX_MSG_LOSS__OFFSET 0x0000000au
#define CYFLD_CAN_RX_MSG_LOSS__SIZE 0x00000001u
#define CYFLD_CAN_TX_MSG__OFFSET 0x0000000bu
#define CYFLD_CAN_TX_MSG__SIZE 0x00000001u
#define CYFLD_CAN_RX_MSG__OFFSET 0x0000000cu
#define CYFLD_CAN_RX_MSG__SIZE 0x00000001u
#define CYFLD_CAN_RTR_MSG__OFFSET 0x0000000du
#define CYFLD_CAN_RTR_MSG__SIZE 0x00000001u
#define CYFLD_CAN_STUCK_AT_0__OFFSET 0x0000000eu
#define CYFLD_CAN_STUCK_AT_0__SIZE 0x00000001u
#define CYFLD_CAN_SST_FAILURE__OFFSET 0x0000000fu
#define CYFLD_CAN_SST_FAILURE__SIZE 0x00000001u
#define CYREG_CAN_INT_EBL 0x402e0004u
#define CYFLD_CAN_GLOBAL_INT_ENBL__OFFSET 0x00000000u
#define CYFLD_CAN_GLOBAL_INT_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_ARB_LOSS_ENBL__OFFSET 0x00000002u
#define CYFLD_CAN_ARB_LOSS_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_OVR_LOAD_ENBL__OFFSET 0x00000003u
#define CYFLD_CAN_OVR_LOAD_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_BIT_ERR_ENBL__OFFSET 0x00000004u
#define CYFLD_CAN_BIT_ERR_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_STUFF_ERR_ENBL__OFFSET 0x00000005u
#define CYFLD_CAN_STUFF_ERR_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_ACK_ERR_ENBL__OFFSET 0x00000006u
#define CYFLD_CAN_ACK_ERR_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_FORM_ERR_ENBL__OFFSET 0x00000007u
#define CYFLD_CAN_FORM_ERR_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_CRC_ERR_ENBL__OFFSET 0x00000008u
#define CYFLD_CAN_CRC_ERR_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_BUS_OFF_ENBL__OFFSET 0x00000009u
#define CYFLD_CAN_BUS_OFF_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_TX_MSG_ENBL__OFFSET 0x0000000bu
#define CYFLD_CAN_TX_MSG_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_RX_MSG_ENBl__OFFSET 0x0000000cu
#define CYFLD_CAN_RX_MSG_ENBl__SIZE 0x00000001u
#define CYFLD_CAN_RTR_MSG_ENBL__OFFSET 0x0000000du
#define CYFLD_CAN_RTR_MSG_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_STUCK_AT_0_ENBL__OFFSET 0x0000000eu
#define CYFLD_CAN_STUCK_AT_0_ENBL__SIZE 0x00000001u
#define CYFLD_CAN_SST_FAILURE_ENBL__OFFSET 0x0000000fu
#define CYFLD_CAN_SST_FAILURE_ENBL__SIZE 0x00000001u
#define CYREG_CAN_BUFFER_STATUS 0x402e0008u
#define CYFLD_CAN_RX0_MSG_AV__OFFSET 0x00000000u
#define CYFLD_CAN_RX0_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX1_MSG_AV__OFFSET 0x00000001u
#define CYFLD_CAN_RX1_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX2_MSG_AV__OFFSET 0x00000002u
#define CYFLD_CAN_RX2_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX3_MSG_AV__OFFSET 0x00000003u
#define CYFLD_CAN_RX3_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX4_MSG_AV__OFFSET 0x00000004u
#define CYFLD_CAN_RX4_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX5_MSG_AV__OFFSET 0x00000005u
#define CYFLD_CAN_RX5_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX6_MSG_AV__OFFSET 0x00000006u
#define CYFLD_CAN_RX6_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX7_MSG_AV__OFFSET 0x00000007u
#define CYFLD_CAN_RX7_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX8_MSG_AV__OFFSET 0x00000008u
#define CYFLD_CAN_RX8_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX9_MSG_AV__OFFSET 0x00000009u
#define CYFLD_CAN_RX9_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX10_MSG_AV__OFFSET 0x0000000au
#define CYFLD_CAN_RX10_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX11_MSG_AV__OFFSET 0x0000000bu
#define CYFLD_CAN_RX11_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX12_MSG_AV__OFFSET 0x0000000cu
#define CYFLD_CAN_RX12_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX13_MSG_AV__OFFSET 0x0000000du
#define CYFLD_CAN_RX13_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX14_MSG_AV__OFFSET 0x0000000eu
#define CYFLD_CAN_RX14_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_RX15_MSG_AV__OFFSET 0x0000000fu
#define CYFLD_CAN_RX15_MSG_AV__SIZE 0x00000001u
#define CYFLD_CAN_TX0_REQ_PEND__OFFSET 0x00000010u
#define CYFLD_CAN_TX0_REQ_PEND__SIZE 0x00000001u
#define CYFLD_CAN_TX1_REQ_PEND__OFFSET 0x00000011u
#define CYFLD_CAN_TX1_REQ_PEND__SIZE 0x00000001u
#define CYFLD_CAN_TX2_REQ_PEND__OFFSET 0x00000012u
#define CYFLD_CAN_TX2_REQ_PEND__SIZE 0x00000001u
#define CYFLD_CAN_TX3_REQ_PEND__OFFSET 0x00000013u
#define CYFLD_CAN_TX3_REQ_PEND__SIZE 0x00000001u
#define CYFLD_CAN_TX4_REQ_PEND__OFFSET 0x00000014u
#define CYFLD_CAN_TX4_REQ_PEND__SIZE 0x00000001u
#define CYFLD_CAN_TX5_REQ_PEND__OFFSET 0x00000015u
#define CYFLD_CAN_TX5_REQ_PEND__SIZE 0x00000001u
#define CYFLD_CAN_TX6_REQ_PEND__OFFSET 0x00000016u
#define CYFLD_CAN_TX6_REQ_PEND__SIZE 0x00000001u
#define CYFLD_CAN_TX7_REQ_PEND__OFFSET 0x00000017u
#define CYFLD_CAN_TX7_REQ_PEND__SIZE 0x00000001u
#define CYREG_CAN_ERROR_STATUS 0x402e000cu
#define CYFLD_CAN_TX_ERR_CNT__OFFSET 0x00000000u
#define CYFLD_CAN_TX_ERR_CNT__SIZE 0x00000008u
#define CYFLD_CAN_RX_ERR_CNT__OFFSET 0x00000008u
#define CYFLD_CAN_RX_ERR_CNT__SIZE 0x00000008u
#define CYFLD_CAN_ERROR_STATE__OFFSET 0x00000010u
#define CYFLD_CAN_ERROR_STATE__SIZE 0x00000002u
#define CYFLD_CAN_TXGTE96__OFFSET 0x00000012u
#define CYFLD_CAN_TXGTE96__SIZE 0x00000001u
#define CYFLD_CAN_RXGTE96__OFFSET 0x00000013u
#define CYFLD_CAN_RXGTE96__SIZE 0x00000001u
#define CYREG_CAN_COMMAND 0x402e0010u
#define CYFLD_CAN_RUN__OFFSET 0x00000000u
#define CYFLD_CAN_RUN__SIZE 0x00000001u
#define CYFLD_CAN_LISTEN__OFFSET 0x00000001u
#define CYFLD_CAN_LISTEN__SIZE 0x00000001u
#define CYFLD_CAN_LOOPBACK_TEST__OFFSET 0x00000002u
#define CYFLD_CAN_LOOPBACK_TEST__SIZE 0x00000001u
#define CYFLD_CAN_SRAM_TEST__OFFSET 0x00000003u
#define CYFLD_CAN_SRAM_TEST__SIZE 0x00000001u
#define CYFLD_CAN_IP_REV_NUMBER__OFFSET 0x00000010u
#define CYFLD_CAN_IP_REV_NUMBER__SIZE 0x00000008u
#define CYFLD_CAN_IP_MINOR_VERSION__OFFSET 0x00000018u
#define CYFLD_CAN_IP_MINOR_VERSION__SIZE 0x00000004u
#define CYFLD_CAN_IP_MAJOR_VERSION__OFFSET 0x0000001cu
#define CYFLD_CAN_IP_MAJOR_VERSION__SIZE 0x00000004u
#define CYREG_CAN_CONFIG 0x402e0014u
#define CYFLD_CAN_EDGE_MODE__OFFSET 0x00000000u
#define CYFLD_CAN_EDGE_MODE__SIZE 0x00000001u
#define CYFLD_CAN_SAMPLING_MODE__OFFSET 0x00000001u
#define CYFLD_CAN_SAMPLING_MODE__SIZE 0x00000001u
#define CYFLD_CAN_CFG_SJW__OFFSET 0x00000002u
#define CYFLD_CAN_CFG_SJW__SIZE 0x00000002u
#define CYFLD_CAN_AUTO_RESTART__OFFSET 0x00000004u
#define CYFLD_CAN_AUTO_RESTART__SIZE 0x00000001u
#define CYFLD_CAN_CFG_TSEG2__OFFSET 0x00000005u
#define CYFLD_CAN_CFG_TSEG2__SIZE 0x00000003u
#define CYFLD_CAN_CFG_TSEG1__OFFSET 0x00000008u
#define CYFLD_CAN_CFG_TSEG1__SIZE 0x00000004u
#define CYFLD_CAN_CFG_ARBITER__OFFSET 0x0000000cu
#define CYFLD_CAN_CFG_ARBITER__SIZE 0x00000001u
#define CYFLD_CAN_SWAP_ENDIAN__OFFSET 0x0000000du
#define CYFLD_CAN_SWAP_ENDIAN__SIZE 0x00000001u
#define CYFLD_CAN_ECR_MODE__OFFSET 0x0000000eu
#define CYFLD_CAN_ECR_MODE__SIZE 0x00000001u
#define CYFLD_CAN_CFG_BITRATE__OFFSET 0x00000010u
#define CYFLD_CAN_CFG_BITRATE__SIZE 0x0000000fu
#define CYREG_CAN_ECR 0x402e0018u
#define CYFLD_CAN_ECR_STATUS__OFFSET 0x00000000u
#define CYFLD_CAN_ECR_STATUS__SIZE 0x00000001u
#define CYFLD_CAN_ERROR_TYPE__OFFSET 0x00000001u
#define CYFLD_CAN_ERROR_TYPE__SIZE 0x00000003u
#define CYFLD_CAN_RX_MODE__OFFSET 0x00000004u
#define CYFLD_CAN_RX_MODE__SIZE 0x00000001u
#define CYFLD_CAN_TX_MODE__OFFSET 0x00000005u
#define CYFLD_CAN_TX_MODE__SIZE 0x00000001u
#define CYFLD_CAN_BIT__OFFSET 0x00000006u
#define CYFLD_CAN_BIT__SIZE 0x00000006u
#define CYFLD_CAN_Field__OFFSET 0x0000000cu
#define CYFLD_CAN_Field__SIZE 0x00000005u
#define CYDEV_CAN_CAN_TX0_BASE 0x402e0020u
#define CYDEV_CAN_CAN_TX0_SIZE 0x00000010u
#define CYREG_CAN_CAN_TX0_CONTROL 0x402e0020u
#define CYFLD_CAN_CAN_TX_TX_REQ__OFFSET 0x00000000u
#define CYFLD_CAN_CAN_TX_TX_REQ__SIZE 0x00000001u
#define CYFLD_CAN_CAN_TX_TX_ABORT__OFFSET 0x00000001u
#define CYFLD_CAN_CAN_TX_TX_ABORT__SIZE 0x00000001u
#define CYFLD_CAN_CAN_TX_TX_INT_EBL__OFFSET 0x00000002u
#define CYFLD_CAN_CAN_TX_TX_INT_EBL__SIZE 0x00000001u
#define CYFLD_CAN_CAN_TX_WPNL__OFFSET 0x00000003u
#define CYFLD_CAN_CAN_TX_WPNL__SIZE 0x00000001u
#define CYFLD_CAN_CAN_TX_DLC__OFFSET 0x00000010u
#define CYFLD_CAN_CAN_TX_DLC__SIZE 0x00000004u
#define CYFLD_CAN_CAN_TX_IDE__OFFSET 0x00000014u
#define CYFLD_CAN_CAN_TX_IDE__SIZE 0x00000001u
#define CYFLD_CAN_CAN_TX_RTR__OFFSET 0x00000015u
#define CYFLD_CAN_CAN_TX_RTR__SIZE 0x00000001u
#define CYFLD_CAN_CAN_TX_WPNH__OFFSET 0x00000017u
#define CYFLD_CAN_CAN_TX_WPNH__SIZE 0x00000001u
#define CYREG_CAN_CAN_TX0_ID 0x402e0024u
#define CYFLD_CAN_CAN_TX_ID__OFFSET 0x00000003u
#define CYFLD_CAN_CAN_TX_ID__SIZE 0x0000001du
#define CYREG_CAN_CAN_TX0_DATA_HIGH 0x402e0028u
#define CYFLD_CAN_CAN_TX_DATA__OFFSET 0x00000000u
#define CYFLD_CAN_CAN_TX_DATA__SIZE 0x00000020u
#define CYREG_CAN_CAN_TX0_DATA_LOW 0x402e002cu
#define CYDEV_CAN_CAN_TX1_BASE 0x402e0030u
#define CYDEV_CAN_CAN_TX1_SIZE 0x00000010u
#define CYREG_CAN_CAN_TX1_CONTROL 0x402e0030u
#define CYREG_CAN_CAN_TX1_ID 0x402e0034u
#define CYREG_CAN_CAN_TX1_DATA_HIGH 0x402e0038u
#define CYREG_CAN_CAN_TX1_DATA_LOW 0x402e003cu
#define CYDEV_CAN_CAN_TX2_BASE 0x402e0040u
#define CYDEV_CAN_CAN_TX2_SIZE 0x00000010u
#define CYREG_CAN_CAN_TX2_CONTROL 0x402e0040u
#define CYREG_CAN_CAN_TX2_ID 0x402e0044u
#define CYREG_CAN_CAN_TX2_DATA_HIGH 0x402e0048u
#define CYREG_CAN_CAN_TX2_DATA_LOW 0x402e004cu
#define CYDEV_CAN_CAN_TX3_BASE 0x402e0050u
#define CYDEV_CAN_CAN_TX3_SIZE 0x00000010u
#define CYREG_CAN_CAN_TX3_CONTROL 0x402e0050u
#define CYREG_CAN_CAN_TX3_ID 0x402e0054u
#define CYREG_CAN_CAN_TX3_DATA_HIGH 0x402e0058u
#define CYREG_CAN_CAN_TX3_DATA_LOW 0x402e005cu
#define CYDEV_CAN_CAN_TX4_BASE 0x402e0060u
#define CYDEV_CAN_CAN_TX4_SIZE 0x00000010u
#define CYREG_CAN_CAN_TX4_CONTROL 0x402e0060u
#define CYREG_CAN_CAN_TX4_ID 0x402e0064u
#define CYREG_CAN_CAN_TX4_DATA_HIGH 0x402e0068u
#define CYREG_CAN_CAN_TX4_DATA_LOW 0x402e006cu
#define CYDEV_CAN_CAN_TX5_BASE 0x402e0070u
#define CYDEV_CAN_CAN_TX5_SIZE 0x00000010u
#define CYREG_CAN_CAN_TX5_CONTROL 0x402e0070u
#define CYREG_CAN_CAN_TX5_ID 0x402e0074u
#define CYREG_CAN_CAN_TX5_DATA_HIGH 0x402e0078u
#define CYREG_CAN_CAN_TX5_DATA_LOW 0x402e007cu
#define CYDEV_CAN_CAN_TX6_BASE 0x402e0080u
#define CYDEV_CAN_CAN_TX6_SIZE 0x00000010u
#define CYREG_CAN_CAN_TX6_CONTROL 0x402e0080u
#define CYREG_CAN_CAN_TX6_ID 0x402e0084u
#define CYREG_CAN_CAN_TX6_DATA_HIGH 0x402e0088u
#define CYREG_CAN_CAN_TX6_DATA_LOW 0x402e008cu
#define CYDEV_CAN_CAN_TX7_BASE 0x402e0090u
#define CYDEV_CAN_CAN_TX7_SIZE 0x00000010u
#define CYREG_CAN_CAN_TX7_CONTROL 0x402e0090u
#define CYREG_CAN_CAN_TX7_ID 0x402e0094u
#define CYREG_CAN_CAN_TX7_DATA_HIGH 0x402e0098u
#define CYREG_CAN_CAN_TX7_DATA_LOW 0x402e009cu
#define CYDEV_CAN_CAN_RX0_BASE 0x402e00a0u
#define CYDEV_CAN_CAN_RX0_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX0_CONTROL 0x402e00a0u
#define CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__OFFSET 0x00000000u
#define CYFLD_CAN_CAN_RX_MSG_AV_RTRSENT__SIZE 0x00000001u
#define CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__OFFSET 0x00000001u
#define CYFLD_CAN_CAN_RX_RTR_REPLY_PEND__SIZE 0x00000001u
#define CYFLD_CAN_CAN_RX_RTR_ABORT__OFFSET 0x00000002u
#define CYFLD_CAN_CAN_RX_RTR_ABORT__SIZE 0x00000001u
#define CYFLD_CAN_CAN_RX_BUFFER_EN__OFFSET 0x00000003u
#define CYFLD_CAN_CAN_RX_BUFFER_EN__SIZE 0x00000001u
#define CYFLD_CAN_CAN_RX_RTR_REPLY__OFFSET 0x00000004u
#define CYFLD_CAN_CAN_RX_RTR_REPLY__SIZE 0x00000001u
#define CYFLD_CAN_CAN_RX_RX_INT_EBL__OFFSET 0x00000005u
#define CYFLD_CAN_CAN_RX_RX_INT_EBL__SIZE 0x00000001u
#define CYFLD_CAN_CAN_RX_LINK_FLAG__OFFSET 0x00000006u
#define CYFLD_CAN_CAN_RX_LINK_FLAG__SIZE 0x00000001u
#define CYFLD_CAN_CAN_RX_WPNL__OFFSET 0x00000007u
#define CYFLD_CAN_CAN_RX_WPNL__SIZE 0x00000001u
#define CYFLD_CAN_CAN_RX_DLC__OFFSET 0x00000010u
#define CYFLD_CAN_CAN_RX_DLC__SIZE 0x00000004u
#define CYFLD_CAN_CAN_RX_IDE_FMT__OFFSET 0x00000014u
#define CYFLD_CAN_CAN_RX_IDE_FMT__SIZE 0x00000001u
#define CYFLD_CAN_CAN_RX_RTR_MSG__OFFSET 0x00000015u
#define CYFLD_CAN_CAN_RX_RTR_MSG__SIZE 0x00000001u
#define CYFLD_CAN_CAN_RX_WPNH__OFFSET 0x00000017u
#define CYFLD_CAN_CAN_RX_WPNH__SIZE 0x00000001u
#define CYREG_CAN_CAN_RX0_ID 0x402e00a4u
#define CYFLD_CAN_CAN_RX_ID__OFFSET 0x00000003u
#define CYFLD_CAN_CAN_RX_ID__SIZE 0x0000001du
#define CYREG_CAN_CAN_RX0_DATA_HIGH 0x402e00a8u
#define CYFLD_CAN_CAN_RX_DATA__OFFSET 0x00000000u
#define CYFLD_CAN_CAN_RX_DATA__SIZE 0x00000020u
#define CYREG_CAN_CAN_RX0_DATA_LOW 0x402e00acu
#define CYREG_CAN_CAN_RX0_AMR 0x402e00b0u
#define CYFLD_CAN_CAN_RX_RTR__OFFSET 0x00000001u
#define CYFLD_CAN_CAN_RX_RTR__SIZE 0x00000001u
#define CYFLD_CAN_CAN_RX_IDE__OFFSET 0x00000002u
#define CYFLD_CAN_CAN_RX_IDE__SIZE 0x00000001u
#define CYREG_CAN_CAN_RX0_ACR 0x402e00b4u
#define CYREG_CAN_CAN_RX0_AMR_DATA 0x402e00b8u
#define CYFLD_CAN_CAN_RX_DATAL__OFFSET 0x00000000u
#define CYFLD_CAN_CAN_RX_DATAL__SIZE 0x00000010u
#define CYREG_CAN_CAN_RX0_ACR_DATA 0x402e00bcu
#define CYDEV_CAN_CAN_RX1_BASE 0x402e00c0u
#define CYDEV_CAN_CAN_RX1_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX1_CONTROL 0x402e00c0u
#define CYREG_CAN_CAN_RX1_ID 0x402e00c4u
#define CYREG_CAN_CAN_RX1_DATA_HIGH 0x402e00c8u
#define CYREG_CAN_CAN_RX1_DATA_LOW 0x402e00ccu
#define CYREG_CAN_CAN_RX1_AMR 0x402e00d0u
#define CYREG_CAN_CAN_RX1_ACR 0x402e00d4u
#define CYREG_CAN_CAN_RX1_AMR_DATA 0x402e00d8u
#define CYREG_CAN_CAN_RX1_ACR_DATA 0x402e00dcu
#define CYDEV_CAN_CAN_RX2_BASE 0x402e00e0u
#define CYDEV_CAN_CAN_RX2_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX2_CONTROL 0x402e00e0u
#define CYREG_CAN_CAN_RX2_ID 0x402e00e4u
#define CYREG_CAN_CAN_RX2_DATA_HIGH 0x402e00e8u
#define CYREG_CAN_CAN_RX2_DATA_LOW 0x402e00ecu
#define CYREG_CAN_CAN_RX2_AMR 0x402e00f0u
#define CYREG_CAN_CAN_RX2_ACR 0x402e00f4u
#define CYREG_CAN_CAN_RX2_AMR_DATA 0x402e00f8u
#define CYREG_CAN_CAN_RX2_ACR_DATA 0x402e00fcu
#define CYDEV_CAN_CAN_RX3_BASE 0x402e0100u
#define CYDEV_CAN_CAN_RX3_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX3_CONTROL 0x402e0100u
#define CYREG_CAN_CAN_RX3_ID 0x402e0104u
#define CYREG_CAN_CAN_RX3_DATA_HIGH 0x402e0108u
#define CYREG_CAN_CAN_RX3_DATA_LOW 0x402e010cu
#define CYREG_CAN_CAN_RX3_AMR 0x402e0110u
#define CYREG_CAN_CAN_RX3_ACR 0x402e0114u
#define CYREG_CAN_CAN_RX3_AMR_DATA 0x402e0118u
#define CYREG_CAN_CAN_RX3_ACR_DATA 0x402e011cu
#define CYDEV_CAN_CAN_RX4_BASE 0x402e0120u
#define CYDEV_CAN_CAN_RX4_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX4_CONTROL 0x402e0120u
#define CYREG_CAN_CAN_RX4_ID 0x402e0124u
#define CYREG_CAN_CAN_RX4_DATA_HIGH 0x402e0128u
#define CYREG_CAN_CAN_RX4_DATA_LOW 0x402e012cu
#define CYREG_CAN_CAN_RX4_AMR 0x402e0130u
#define CYREG_CAN_CAN_RX4_ACR 0x402e0134u
#define CYREG_CAN_CAN_RX4_AMR_DATA 0x402e0138u
#define CYREG_CAN_CAN_RX4_ACR_DATA 0x402e013cu
#define CYDEV_CAN_CAN_RX5_BASE 0x402e0140u
#define CYDEV_CAN_CAN_RX5_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX5_CONTROL 0x402e0140u
#define CYREG_CAN_CAN_RX5_ID 0x402e0144u
#define CYREG_CAN_CAN_RX5_DATA_HIGH 0x402e0148u
#define CYREG_CAN_CAN_RX5_DATA_LOW 0x402e014cu
#define CYREG_CAN_CAN_RX5_AMR 0x402e0150u
#define CYREG_CAN_CAN_RX5_ACR 0x402e0154u
#define CYREG_CAN_CAN_RX5_AMR_DATA 0x402e0158u
#define CYREG_CAN_CAN_RX5_ACR_DATA 0x402e015cu
#define CYDEV_CAN_CAN_RX6_BASE 0x402e0160u
#define CYDEV_CAN_CAN_RX6_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX6_CONTROL 0x402e0160u
#define CYREG_CAN_CAN_RX6_ID 0x402e0164u
#define CYREG_CAN_CAN_RX6_DATA_HIGH 0x402e0168u
#define CYREG_CAN_CAN_RX6_DATA_LOW 0x402e016cu
#define CYREG_CAN_CAN_RX6_AMR 0x402e0170u
#define CYREG_CAN_CAN_RX6_ACR 0x402e0174u
#define CYREG_CAN_CAN_RX6_AMR_DATA 0x402e0178u
#define CYREG_CAN_CAN_RX6_ACR_DATA 0x402e017cu
#define CYDEV_CAN_CAN_RX7_BASE 0x402e0180u
#define CYDEV_CAN_CAN_RX7_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX7_CONTROL 0x402e0180u
#define CYREG_CAN_CAN_RX7_ID 0x402e0184u
#define CYREG_CAN_CAN_RX7_DATA_HIGH 0x402e0188u
#define CYREG_CAN_CAN_RX7_DATA_LOW 0x402e018cu
#define CYREG_CAN_CAN_RX7_AMR 0x402e0190u
#define CYREG_CAN_CAN_RX7_ACR 0x402e0194u
#define CYREG_CAN_CAN_RX7_AMR_DATA 0x402e0198u
#define CYREG_CAN_CAN_RX7_ACR_DATA 0x402e019cu
#define CYDEV_CAN_CAN_RX8_BASE 0x402e01a0u
#define CYDEV_CAN_CAN_RX8_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX8_CONTROL 0x402e01a0u
#define CYREG_CAN_CAN_RX8_ID 0x402e01a4u
#define CYREG_CAN_CAN_RX8_DATA_HIGH 0x402e01a8u
#define CYREG_CAN_CAN_RX8_DATA_LOW 0x402e01acu
#define CYREG_CAN_CAN_RX8_AMR 0x402e01b0u
#define CYREG_CAN_CAN_RX8_ACR 0x402e01b4u
#define CYREG_CAN_CAN_RX8_AMR_DATA 0x402e01b8u
#define CYREG_CAN_CAN_RX8_ACR_DATA 0x402e01bcu
#define CYDEV_CAN_CAN_RX9_BASE 0x402e01c0u
#define CYDEV_CAN_CAN_RX9_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX9_CONTROL 0x402e01c0u
#define CYREG_CAN_CAN_RX9_ID 0x402e01c4u
#define CYREG_CAN_CAN_RX9_DATA_HIGH 0x402e01c8u
#define CYREG_CAN_CAN_RX9_DATA_LOW 0x402e01ccu
#define CYREG_CAN_CAN_RX9_AMR 0x402e01d0u
#define CYREG_CAN_CAN_RX9_ACR 0x402e01d4u
#define CYREG_CAN_CAN_RX9_AMR_DATA 0x402e01d8u
#define CYREG_CAN_CAN_RX9_ACR_DATA 0x402e01dcu
#define CYDEV_CAN_CAN_RX10_BASE 0x402e01e0u
#define CYDEV_CAN_CAN_RX10_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX10_CONTROL 0x402e01e0u
#define CYREG_CAN_CAN_RX10_ID 0x402e01e4u
#define CYREG_CAN_CAN_RX10_DATA_HIGH 0x402e01e8u
#define CYREG_CAN_CAN_RX10_DATA_LOW 0x402e01ecu
#define CYREG_CAN_CAN_RX10_AMR 0x402e01f0u
#define CYREG_CAN_CAN_RX10_ACR 0x402e01f4u
#define CYREG_CAN_CAN_RX10_AMR_DATA 0x402e01f8u
#define CYREG_CAN_CAN_RX10_ACR_DATA 0x402e01fcu
#define CYDEV_CAN_CAN_RX11_BASE 0x402e0200u
#define CYDEV_CAN_CAN_RX11_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX11_CONTROL 0x402e0200u
#define CYREG_CAN_CAN_RX11_ID 0x402e0204u
#define CYREG_CAN_CAN_RX11_DATA_HIGH 0x402e0208u
#define CYREG_CAN_CAN_RX11_DATA_LOW 0x402e020cu
#define CYREG_CAN_CAN_RX11_AMR 0x402e0210u
#define CYREG_CAN_CAN_RX11_ACR 0x402e0214u
#define CYREG_CAN_CAN_RX11_AMR_DATA 0x402e0218u
#define CYREG_CAN_CAN_RX11_ACR_DATA 0x402e021cu
#define CYDEV_CAN_CAN_RX12_BASE 0x402e0220u
#define CYDEV_CAN_CAN_RX12_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX12_CONTROL 0x402e0220u
#define CYREG_CAN_CAN_RX12_ID 0x402e0224u
#define CYREG_CAN_CAN_RX12_DATA_HIGH 0x402e0228u
#define CYREG_CAN_CAN_RX12_DATA_LOW 0x402e022cu
#define CYREG_CAN_CAN_RX12_AMR 0x402e0230u
#define CYREG_CAN_CAN_RX12_ACR 0x402e0234u
#define CYREG_CAN_CAN_RX12_AMR_DATA 0x402e0238u
#define CYREG_CAN_CAN_RX12_ACR_DATA 0x402e023cu
#define CYDEV_CAN_CAN_RX13_BASE 0x402e0240u
#define CYDEV_CAN_CAN_RX13_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX13_CONTROL 0x402e0240u
#define CYREG_CAN_CAN_RX13_ID 0x402e0244u
#define CYREG_CAN_CAN_RX13_DATA_HIGH 0x402e0248u
#define CYREG_CAN_CAN_RX13_DATA_LOW 0x402e024cu
#define CYREG_CAN_CAN_RX13_AMR 0x402e0250u
#define CYREG_CAN_CAN_RX13_ACR 0x402e0254u
#define CYREG_CAN_CAN_RX13_AMR_DATA 0x402e0258u
#define CYREG_CAN_CAN_RX13_ACR_DATA 0x402e025cu
#define CYDEV_CAN_CAN_RX14_BASE 0x402e0260u
#define CYDEV_CAN_CAN_RX14_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX14_CONTROL 0x402e0260u
#define CYREG_CAN_CAN_RX14_ID 0x402e0264u
#define CYREG_CAN_CAN_RX14_DATA_HIGH 0x402e0268u
#define CYREG_CAN_CAN_RX14_DATA_LOW 0x402e026cu
#define CYREG_CAN_CAN_RX14_AMR 0x402e0270u
#define CYREG_CAN_CAN_RX14_ACR 0x402e0274u
#define CYREG_CAN_CAN_RX14_AMR_DATA 0x402e0278u
#define CYREG_CAN_CAN_RX14_ACR_DATA 0x402e027cu
#define CYDEV_CAN_CAN_RX15_BASE 0x402e0280u
#define CYDEV_CAN_CAN_RX15_SIZE 0x00000020u
#define CYREG_CAN_CAN_RX15_CONTROL 0x402e0280u
#define CYREG_CAN_CAN_RX15_ID 0x402e0284u
#define CYREG_CAN_CAN_RX15_DATA_HIGH 0x402e0288u
#define CYREG_CAN_CAN_RX15_DATA_LOW 0x402e028cu
#define CYREG_CAN_CAN_RX15_AMR 0x402e0290u
#define CYREG_CAN_CAN_RX15_ACR 0x402e0294u
#define CYREG_CAN_CAN_RX15_AMR_DATA 0x402e0298u
#define CYREG_CAN_CAN_RX15_ACR_DATA 0x402e029cu
#define CYREG_CAN_CNTL 0x402e0400u
#define CYFLD_CAN_TT_ENABLE__OFFSET 0x00000000u
#define CYFLD_CAN_TT_ENABLE__SIZE 0x00000001u
#define CYFLD_CAN_IP_ENABLE__OFFSET 0x0000001fu
#define CYFLD_CAN_IP_ENABLE__SIZE 0x00000001u
#define CYREG_CAN_TTCAN_COUNTER 0x402e0404u
#define CYFLD_CAN_LOCAL_TIME__OFFSET 0x00000010u
#define CYFLD_CAN_LOCAL_TIME__SIZE 0x00000010u
#define CYREG_CAN_TTCAN_COMPARE 0x402e0408u
#define CYFLD_CAN_TIME_MARK__OFFSET 0x00000010u
#define CYFLD_CAN_TIME_MARK__SIZE 0x00000010u
#define CYREG_CAN_TTCAN_CAPTURE 0x402e040cu
#define CYFLD_CAN_SYNC_MARK__OFFSET 0x00000010u
#define CYFLD_CAN_SYNC_MARK__SIZE 0x00000010u
#define CYREG_CAN_TTCAN_TIMING 0x402e0410u
#define CYREG_CAN_INTR_CAN 0x402e0414u
#define CYFLD_CAN_INT_STATUS__OFFSET 0x00000000u
#define CYFLD_CAN_INT_STATUS__SIZE 0x00000001u
#define CYFLD_CAN_TT_COMPARE__OFFSET 0x00000001u
#define CYFLD_CAN_TT_COMPARE__SIZE 0x00000001u
#define CYFLD_CAN_TT_CAPTURE__OFFSET 0x00000002u
#define CYFLD_CAN_TT_CAPTURE__SIZE 0x00000001u
#define CYREG_CAN_INTR_CAN_SET 0x402e0418u
#define CYREG_CAN_INTR_CAN_MASK 0x402e041cu
#define CYREG_CAN_INTR_CAN_MASKED 0x402e0420u
#define CYDEV_EXCO_BASE 0x402f0000u
#define CYDEV_EXCO_SIZE 0x00010000u
#define CYREG_EXCO_CLK_SELECT 0x402f0000u
#define CYFLD_EXCO_CLK_SELECT__OFFSET 0x00000000u
#define CYFLD_EXCO_CLK_SELECT__SIZE 0x00000001u
#define CYFLD_EXCO_REF_SEL__OFFSET 0x00000001u
#define CYFLD_EXCO_REF_SEL__SIZE 0x00000001u
#define CYREG_EXCO_ECO_CONFIG 0x402f0008u
#define CYFLD_EXCO_CLK_EN__OFFSET 0x00000000u
#define CYFLD_EXCO_CLK_EN__SIZE 0x00000001u
#define CYFLD_EXCO_AGC_EN__OFFSET 0x00000001u
#define CYFLD_EXCO_AGC_EN__SIZE 0x00000001u
#define CYFLD_EXCO_ENABLE__OFFSET 0x0000001fu
#define CYFLD_EXCO_ENABLE__SIZE 0x00000001u
#define CYREG_EXCO_ECO_STATUS 0x402f000cu
#define CYFLD_EXCO_WATCHDOG_ERROR__OFFSET 0x00000000u
#define CYFLD_EXCO_WATCHDOG_ERROR__SIZE 0x00000001u
#define CYREG_EXCO_PLL_CONFIG 0x402f0014u
#define CYFLD_EXCO_FEEDBACK_DIV__OFFSET 0x00000000u
#define CYFLD_EXCO_FEEDBACK_DIV__SIZE 0x00000008u
#define CYFLD_EXCO_REFERENCE_DIV__OFFSET 0x00000008u
#define CYFLD_EXCO_REFERENCE_DIV__SIZE 0x00000006u
#define CYFLD_EXCO_OUTPUT_DIV__OFFSET 0x0000000eu
#define CYFLD_EXCO_OUTPUT_DIV__SIZE 0x00000002u
#define CYVAL_EXCO_OUTPUT_DIV_PASS 0x00000000u
#define CYVAL_EXCO_OUTPUT_DIV_DIV2 0x00000001u
#define CYVAL_EXCO_OUTPUT_DIV_DIV4 0x00000002u
#define CYVAL_EXCO_OUTPUT_DIV_DIV8 0x00000003u
#define CYFLD_EXCO_ICP_SEL__OFFSET 0x00000010u
#define CYFLD_EXCO_ICP_SEL__SIZE 0x00000003u
#define CYFLD_EXCO_BYPASS_SEL__OFFSET 0x00000014u
#define CYFLD_EXCO_BYPASS_SEL__SIZE 0x00000002u
#define CYVAL_EXCO_BYPASS_SEL_AUTO 0x00000000u
#define CYVAL_EXCO_BYPASS_SEL_AUTO1 0x00000001u
#define CYVAL_EXCO_BYPASS_SEL_PLL_REF 0x00000002u
#define CYVAL_EXCO_BYPASS_SEL_PLL_OUT 0x00000003u
#define CYFLD_EXCO_ISOLATE_N__OFFSET 0x0000001eu
#define CYFLD_EXCO_ISOLATE_N__SIZE 0x00000001u
#define CYREG_EXCO_PLL_STATUS 0x402f0018u
#define CYFLD_EXCO_LOCKED__OFFSET 0x00000000u
#define CYFLD_EXCO_LOCKED__SIZE 0x00000001u
#define CYREG_EXCO_PLL_TEST 0x402f001cu
#define CYFLD_EXCO_TEST_MODE__OFFSET 0x00000000u
#define CYFLD_EXCO_TEST_MODE__SIZE 0x00000003u
#define CYVAL_EXCO_TEST_MODE_NORMAL 0x00000000u
#define CYVAL_EXCO_TEST_MODE_TEST_VC_LKG 0x00000001u
#define CYVAL_EXCO_TEST_MODE_TEST_CP_DN 0x00000002u
#define CYVAL_EXCO_TEST_MODE_TEST_CP_UP 0x00000003u
#define CYVAL_EXCO_TEST_MODE_USER_EXT_FL 0x00000004u
#define CYVAL_EXCO_TEST_MODE_TEST_CTR_PQ 0x00000005u
#define CYVAL_EXCO_TEST_MODE_TEST_LD_DLY 0x00000006u
#define CYVAL_EXCO_TEST_MODE_TEST_CTR_ALT 0x00000007u
#define CYFLD_EXCO_FAST_LOCK_EN__OFFSET 0x00000003u
#define CYFLD_EXCO_FAST_LOCK_EN__SIZE 0x00000001u
#define CYFLD_EXCO_UNLOCK_OCCURRED__OFFSET 0x00000004u
#define CYFLD_EXCO_UNLOCK_OCCURRED__SIZE 0x00000001u
#define CYREG_EXCO_EXCO_PGM_CLK 0x402f0020u
#define CYFLD_EXCO_CLK_ECO__OFFSET 0x00000001u
#define CYFLD_EXCO_CLK_ECO__SIZE 0x00000001u
#define CYFLD_EXCO_CLK_PLL0_IN__OFFSET 0x00000002u
#define CYFLD_EXCO_CLK_PLL0_IN__SIZE 0x00000001u
#define CYFLD_EXCO_CLK_PLL0_OUT__OFFSET 0x00000003u
#define CYFLD_EXCO_CLK_PLL0_OUT__SIZE 0x00000001u
#define CYFLD_EXCO_EN_CLK_PLL0__OFFSET 0x00000004u
#define CYFLD_EXCO_EN_CLK_PLL0__SIZE 0x00000001u
#define CYREG_EXCO_ECO_TRIM0 0x402fff00u
#define CYFLD_EXCO_WDTRIM__OFFSET 0x00000000u
#define CYFLD_EXCO_WDTRIM__SIZE 0x00000002u
#define CYFLD_EXCO_ATRIM__OFFSET 0x00000002u
#define CYFLD_EXCO_ATRIM__SIZE 0x00000003u
#define CYREG_EXCO_ECO_TRIM1 0x402fff04u
#define CYFLD_EXCO_FTRIM__OFFSET 0x00000000u
#define CYFLD_EXCO_FTRIM__SIZE 0x00000002u
#define CYFLD_EXCO_RTRIM__OFFSET 0x00000002u
#define CYFLD_EXCO_RTRIM__SIZE 0x00000002u
#define CYFLD_EXCO_GTRIM__OFFSET 0x00000004u
#define CYFLD_EXCO_GTRIM__SIZE 0x00000002u
#define CYREG_EXCO_ECO_TRIM2 0x402fff08u
#define CYFLD_EXCO_ITRIM__OFFSET 0x00000000u
#define CYFLD_EXCO_ITRIM__SIZE 0x00000006u
#define CYREG_EXCO_PLL_TRIM 0x402fff0cu
#define CYFLD_EXCO_VCO_GAIN__OFFSET 0x00000000u
#define CYFLD_EXCO_VCO_GAIN__SIZE 0x00000002u
#define CYFLD_EXCO_LOCK_WINDOW__OFFSET 0x00000002u
#define CYFLD_EXCO_LOCK_WINDOW__SIZE 0x00000002u
#define CYVAL_EXCO_LOCK_WINDOW_DELAY_25NS 0x00000000u
#define CYVAL_EXCO_LOCK_WINDOW_DELAY_50NS 0x00000001u
#define CYVAL_EXCO_LOCK_WINDOW_DELAY_75NS 0x00000002u
#define CYVAL_EXCO_LOCK_WINDOW_DELAY_100NS 0x00000003u
#define CYFLD_EXCO_LOCK_DELAY__OFFSET 0x00000004u
#define CYFLD_EXCO_LOCK_DELAY__SIZE 0x00000002u
#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_16 0x00000000u
#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_32 0x00000001u
#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_48 0x00000002u
#define CYVAL_EXCO_LOCK_DELAY_PFD_CLK_64 0x00000003u
#define CYDEV_CTBM0_BASE 0x40300000u
#define CYDEV_CTBM0_SIZE 0x00010000u
#define CYREG_CTBM0_CTB_CTRL 0x40300000u
#define CYFLD_CTBM_DEEPSLEEP_ON__OFFSET 0x0000001eu
#define CYFLD_CTBM_DEEPSLEEP_ON__SIZE 0x00000001u
#define CYFLD_CTBM_ENABLED__OFFSET 0x0000001fu
#define CYFLD_CTBM_ENABLED__SIZE 0x00000001u
#define CYREG_CTBM0_OA_RES0_CTRL 0x40300004u
#define CYFLD_CTBM_OA0_PWR_MODE__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_PWR_MODE__SIZE 0x00000002u
#define CYVAL_CTBM_OA0_PWR_MODE_OFF 0x00000000u
#define CYVAL_CTBM_OA0_PWR_MODE_LOW 0x00000001u
#define CYVAL_CTBM_OA0_PWR_MODE_MEDIUM 0x00000002u
#define CYVAL_CTBM_OA0_PWR_MODE_HIGH 0x00000003u
#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__OFFSET 0x00000002u
#define CYFLD_CTBM_OA0_DRIVE_STR_SEL__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_COMP_EN__OFFSET 0x00000004u
#define CYFLD_CTBM_OA0_COMP_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_HYST_EN__OFFSET 0x00000005u
#define CYFLD_CTBM_OA0_HYST_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__OFFSET 0x00000006u
#define CYFLD_CTBM_OA0_BYPASS_DSI_SYNC__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_DSI_LEVEL__OFFSET 0x00000007u
#define CYFLD_CTBM_OA0_DSI_LEVEL__SIZE 0x00000001u
#define CYFLD_CTBM_OA0_COMPINT__OFFSET 0x00000008u
#define CYFLD_CTBM_OA0_COMPINT__SIZE 0x00000002u
#define CYVAL_CTBM_OA0_COMPINT_DISABLE 0x00000000u
#define CYVAL_CTBM_OA0_COMPINT_RISING 0x00000001u
#define CYVAL_CTBM_OA0_COMPINT_FALLING 0x00000002u
#define CYVAL_CTBM_OA0_COMPINT_BOTH 0x00000003u
#define CYFLD_CTBM_OA0_PUMP_EN__OFFSET 0x0000000bu
#define CYFLD_CTBM_OA0_PUMP_EN__SIZE 0x00000001u
#define CYREG_CTBM0_OA_RES1_CTRL 0x40300008u
#define CYFLD_CTBM_OA1_PWR_MODE__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_PWR_MODE__SIZE 0x00000002u
#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__OFFSET 0x00000002u
#define CYFLD_CTBM_OA1_DRIVE_STR_SEL__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_COMP_EN__OFFSET 0x00000004u
#define CYFLD_CTBM_OA1_COMP_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_HYST_EN__OFFSET 0x00000005u
#define CYFLD_CTBM_OA1_HYST_EN__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__OFFSET 0x00000006u
#define CYFLD_CTBM_OA1_BYPASS_DSI_SYNC__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_DSI_LEVEL__OFFSET 0x00000007u
#define CYFLD_CTBM_OA1_DSI_LEVEL__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_COMPINT__OFFSET 0x00000008u
#define CYFLD_CTBM_OA1_COMPINT__SIZE 0x00000002u
#define CYVAL_CTBM_OA1_COMPINT_DISABLE 0x00000000u
#define CYVAL_CTBM_OA1_COMPINT_RISING 0x00000001u
#define CYVAL_CTBM_OA1_COMPINT_FALLING 0x00000002u
#define CYVAL_CTBM_OA1_COMPINT_BOTH 0x00000003u
#define CYFLD_CTBM_OA1_PUMP_EN__OFFSET 0x0000000bu
#define CYFLD_CTBM_OA1_PUMP_EN__SIZE 0x00000001u
#define CYREG_CTBM0_COMP_STAT 0x4030000cu
#define CYFLD_CTBM_OA0_COMP__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_COMP__SIZE 0x00000001u
#define CYFLD_CTBM_OA1_COMP__OFFSET 0x00000010u
#define CYFLD_CTBM_OA1_COMP__SIZE 0x00000001u
#define CYREG_CTBM0_INTR 0x40300020u
#define CYFLD_CTBM_COMP0__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1__SIZE 0x00000001u
#define CYREG_CTBM0_INTR_SET 0x40300024u
#define CYFLD_CTBM_COMP0_SET__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0_SET__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1_SET__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1_SET__SIZE 0x00000001u
#define CYREG_CTBM0_INTR_MASK 0x40300028u
#define CYFLD_CTBM_COMP0_MASK__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0_MASK__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1_MASK__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1_MASK__SIZE 0x00000001u
#define CYREG_CTBM0_INTR_MASKED 0x4030002cu
#define CYFLD_CTBM_COMP0_MASKED__OFFSET 0x00000000u
#define CYFLD_CTBM_COMP0_MASKED__SIZE 0x00000001u
#define CYFLD_CTBM_COMP1_MASKED__OFFSET 0x00000001u
#define CYFLD_CTBM_COMP1_MASKED__SIZE 0x00000001u
#define CYREG_CTBM0_DFT_CTRL 0x40300030u
#define CYFLD_CTBM_DFT_MODE__OFFSET 0x00000000u
#define CYFLD_CTBM_DFT_MODE__SIZE 0x00000003u
#define CYFLD_CTBM_DFT_EN__OFFSET 0x0000001fu
#define CYFLD_CTBM_DFT_EN__SIZE 0x00000001u
#define CYREG_CTBM0_OA0_SW 0x40300080u
#define CYFLD_CTBM_OA0P_A00__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0P_A00__SIZE 0x00000001u
#define CYFLD_CTBM_OA0P_A20__OFFSET 0x00000002u
#define CYFLD_CTBM_OA0P_A20__SIZE 0x00000001u
#define CYFLD_CTBM_OA0P_A30__OFFSET 0x00000003u
#define CYFLD_CTBM_OA0P_A30__SIZE 0x00000001u
#define CYFLD_CTBM_OA0M_A11__OFFSET 0x00000008u
#define CYFLD_CTBM_OA0M_A11__SIZE 0x00000001u
#define CYFLD_CTBM_OA0M_A81__OFFSET 0x0000000eu
#define CYFLD_CTBM_OA0M_A81__SIZE 0x00000001u
#define CYFLD_CTBM_OA0O_D51__OFFSET 0x00000012u
#define CYFLD_CTBM_OA0O_D51__SIZE 0x00000001u
#define CYFLD_CTBM_OA0O_D81__OFFSET 0x00000015u
#define CYFLD_CTBM_OA0O_D81__SIZE 0x00000001u
#define CYREG_CTBM0_OA0_SW_CLEAR 0x40300084u
#define CYREG_CTBM0_OA1_SW 0x40300088u
#define CYFLD_CTBM_OA1P_A03__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1P_A03__SIZE 0x00000001u
#define CYFLD_CTBM_OA1P_A13__OFFSET 0x00000001u
#define CYFLD_CTBM_OA1P_A13__SIZE 0x00000001u
#define CYFLD_CTBM_OA1P_A43__OFFSET 0x00000004u
#define CYFLD_CTBM_OA1P_A43__SIZE 0x00000001u
#define CYFLD_CTBM_OA1M_A22__OFFSET 0x00000008u
#define CYFLD_CTBM_OA1M_A22__SIZE 0x00000001u
#define CYFLD_CTBM_OA1M_A82__OFFSET 0x0000000eu
#define CYFLD_CTBM_OA1M_A82__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D52__OFFSET 0x00000012u
#define CYFLD_CTBM_OA1O_D52__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D62__OFFSET 0x00000013u
#define CYFLD_CTBM_OA1O_D62__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D82__OFFSET 0x00000015u
#define CYFLD_CTBM_OA1O_D82__SIZE 0x00000001u
#define CYREG_CTBM0_OA1_SW_CLEAR 0x4030008cu
#define CYREG_CTBM0_CTB_SW_HW_CTRL 0x403000c0u
#define CYFLD_CTBM_P2_HW_CTRL__OFFSET 0x00000002u
#define CYFLD_CTBM_P2_HW_CTRL__SIZE 0x00000001u
#define CYFLD_CTBM_P3_HW_CTRL__OFFSET 0x00000003u
#define CYFLD_CTBM_P3_HW_CTRL__SIZE 0x00000001u
#define CYREG_CTBM0_CTB_SW_STATUS 0x403000c4u
#define CYFLD_CTBM_OA0O_D51_STAT__OFFSET 0x0000001cu
#define CYFLD_CTBM_OA0O_D51_STAT__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D52_STAT__OFFSET 0x0000001du
#define CYFLD_CTBM_OA1O_D52_STAT__SIZE 0x00000001u
#define CYFLD_CTBM_OA1O_D62_STAT__OFFSET 0x0000001eu
#define CYFLD_CTBM_OA1O_D62_STAT__SIZE 0x00000001u
#define CYREG_CTBM0_OA0_OFFSET_TRIM 0x40300f00u
#define CYFLD_CTBM_OA0_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM0_OA0_SLOPE_OFFSET_TRIM 0x40300f04u
#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_SLOPE_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM0_OA0_COMP_TRIM 0x40300f08u
#define CYFLD_CTBM_OA0_COMP_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA0_COMP_TRIM__SIZE 0x00000002u
#define CYREG_CTBM0_OA1_OFFSET_TRIM 0x40300f0cu
#define CYFLD_CTBM_OA1_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM0_OA1_SLOPE_OFFSET_TRIM 0x40300f10u
#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_SLOPE_OFFSET_TRIM__SIZE 0x00000006u
#define CYREG_CTBM0_OA1_COMP_TRIM 0x40300f14u
#define CYFLD_CTBM_OA1_COMP_TRIM__OFFSET 0x00000000u
#define CYFLD_CTBM_OA1_COMP_TRIM__SIZE 0x00000002u
#define CYDEV_SAR_BASE 0x403a0000u
#define CYDEV_SAR_SIZE 0x00010000u
#define CYREG_SAR_CTRL 0x403a0000u
#define CYFLD_SAR_VREF_SEL__OFFSET 0x00000004u
#define CYFLD_SAR_VREF_SEL__SIZE 0x00000003u
#define CYVAL_SAR_VREF_SEL_VREF0 0x00000000u
#define CYVAL_SAR_VREF_SEL_VREF1 0x00000001u
#define CYVAL_SAR_VREF_SEL_VREF2 0x00000002u
#define CYVAL_SAR_VREF_SEL_VREF_AROUTE 0x00000003u
#define CYVAL_SAR_VREF_SEL_VBGR 0x00000004u
#define CYVAL_SAR_VREF_SEL_VREF_EXT 0x00000005u
#define CYVAL_SAR_VREF_SEL_VDDA_DIV_2 0x00000006u
#define CYVAL_SAR_VREF_SEL_VDDA 0x00000007u
#define CYFLD_SAR_VREF_BYP_CAP_EN__OFFSET 0x00000007u
#define CYFLD_SAR_VREF_BYP_CAP_EN__SIZE 0x00000001u
#define CYFLD_SAR_NEG_SEL__OFFSET 0x00000009u
#define CYFLD_SAR_NEG_SEL__SIZE 0x00000003u
#define CYVAL_SAR_NEG_SEL_VSSA_KELVIN 0x00000000u
#define CYVAL_SAR_NEG_SEL_ART_VSSA 0x00000001u
#define CYVAL_SAR_NEG_SEL_P1 0x00000002u
#define CYVAL_SAR_NEG_SEL_P3 0x00000003u
#define CYVAL_SAR_NEG_SEL_P5 0x00000004u
#define CYVAL_SAR_NEG_SEL_P7 0x00000005u
#define CYVAL_SAR_NEG_SEL_ACORE 0x00000006u
#define CYVAL_SAR_NEG_SEL_VREF 0x00000007u
#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__OFFSET 0x0000000du
#define CYFLD_SAR_SAR_HW_CTRL_NEGVREF__SIZE 0x00000001u
#define CYFLD_SAR_PWR_CTRL_VREF__OFFSET 0x0000000eu
#define CYFLD_SAR_PWR_CTRL_VREF__SIZE 0x00000002u
#define CYVAL_SAR_PWR_CTRL_VREF_NORMAL_PWR 0x00000000u
#define CYVAL_SAR_PWR_CTRL_VREF_HALF_PWR 0x00000001u
#define CYVAL_SAR_PWR_CTRL_VREF_THIRD_PWR 0x00000002u
#define CYVAL_SAR_PWR_CTRL_VREF_QUARTER_PWR 0x00000003u
#define CYFLD_SAR_SPARE__OFFSET 0x00000010u
#define CYFLD_SAR_SPARE__SIZE 0x00000004u
#define CYFLD_SAR_BOOSTPUMP_EN__OFFSET 0x00000014u
#define CYFLD_SAR_BOOSTPUMP_EN__SIZE 0x00000001u
#define CYFLD_SAR_ICONT_LV__OFFSET 0x00000018u
#define CYFLD_SAR_ICONT_LV__SIZE 0x00000002u
#define CYVAL_SAR_ICONT_LV_NORMAL_PWR 0x00000000u
#define CYVAL_SAR_ICONT_LV_HALF_PWR 0x00000001u
#define CYVAL_SAR_ICONT_LV_MORE_PWR 0x00000002u
#define CYVAL_SAR_ICONT_LV_QUARTER_PWR 0x00000003u
#define CYFLD_SAR_DEEPSLEEP_ON__OFFSET 0x0000001bu
#define CYFLD_SAR_DEEPSLEEP_ON__SIZE 0x00000001u
#define CYFLD_SAR_DSI_SYNC_CONFIG__OFFSET 0x0000001cu
#define CYFLD_SAR_DSI_SYNC_CONFIG__SIZE 0x00000001u
#define CYFLD_SAR_DSI_MODE__OFFSET 0x0000001du
#define CYFLD_SAR_DSI_MODE__SIZE 0x00000001u
#define CYFLD_SAR_SWITCH_DISABLE__OFFSET 0x0000001eu
#define CYFLD_SAR_SWITCH_DISABLE__SIZE 0x00000001u
#define CYFLD_SAR_ENABLED__OFFSET 0x0000001fu
#define CYFLD_SAR_ENABLED__SIZE 0x00000001u
#define CYREG_SAR_SAMPLE_CTRL 0x403a0004u
#define CYFLD_SAR_SUB_RESOLUTION__OFFSET 0x00000000u
#define CYFLD_SAR_SUB_RESOLUTION__SIZE 0x00000001u
#define CYVAL_SAR_SUB_RESOLUTION_8B 0x00000000u
#define CYVAL_SAR_SUB_RESOLUTION_10B 0x00000001u
#define CYFLD_SAR_LEFT_ALIGN__OFFSET 0x00000001u
#define CYFLD_SAR_LEFT_ALIGN__SIZE 0x00000001u
#define CYFLD_SAR_SINGLE_ENDED_SIGNED__OFFSET 0x00000002u
#define CYFLD_SAR_SINGLE_ENDED_SIGNED__SIZE 0x00000001u
#define CYVAL_SAR_SINGLE_ENDED_SIGNED_UNSIGNED 0x00000000u
#define CYVAL_SAR_SINGLE_ENDED_SIGNED_SIGNED 0x00000001u
#define CYFLD_SAR_DIFFERENTIAL_SIGNED__OFFSET 0x00000003u
#define CYFLD_SAR_DIFFERENTIAL_SIGNED__SIZE 0x00000001u
#define CYVAL_SAR_DIFFERENTIAL_SIGNED_UNSIGNED 0x00000000u
#define CYVAL_SAR_DIFFERENTIAL_SIGNED_SIGNED 0x00000001u
#define CYFLD_SAR_AVG_CNT__OFFSET 0x00000004u
#define CYFLD_SAR_AVG_CNT__SIZE 0x00000003u
#define CYFLD_SAR_AVG_SHIFT__OFFSET 0x00000007u
#define CYFLD_SAR_AVG_SHIFT__SIZE 0x00000001u
#define CYFLD_SAR_CONTINUOUS__OFFSET 0x00000010u
#define CYFLD_SAR_CONTINUOUS__SIZE 0x00000001u
#define CYFLD_SAR_DSI_TRIGGER_EN__OFFSET 0x00000011u
#define CYFLD_SAR_DSI_TRIGGER_EN__SIZE 0x00000001u
#define CYFLD_SAR_DSI_TRIGGER_LEVEL__OFFSET 0x00000012u
#define CYFLD_SAR_DSI_TRIGGER_LEVEL__SIZE 0x00000001u
#define CYFLD_SAR_DSI_SYNC_TRIGGER__OFFSET 0x00000013u
#define CYFLD_SAR_DSI_SYNC_TRIGGER__SIZE 0x00000001u
#define CYFLD_SAR_EOS_DSI_OUT_EN__OFFSET 0x0000001fu
#define CYFLD_SAR_EOS_DSI_OUT_EN__SIZE 0x00000001u
#define CYREG_SAR_SAMPLE_TIME01 0x403a0010u
#define CYFLD_SAR_SAMPLE_TIME0__OFFSET 0x00000000u
#define CYFLD_SAR_SAMPLE_TIME0__SIZE 0x0000000au
#define CYFLD_SAR_SAMPLE_TIME1__OFFSET 0x00000010u
#define CYFLD_SAR_SAMPLE_TIME1__SIZE 0x0000000au
#define CYREG_SAR_SAMPLE_TIME23 0x403a0014u
#define CYFLD_SAR_SAMPLE_TIME2__OFFSET 0x00000000u
#define CYFLD_SAR_SAMPLE_TIME2__SIZE 0x0000000au
#define CYFLD_SAR_SAMPLE_TIME3__OFFSET 0x00000010u
#define CYFLD_SAR_SAMPLE_TIME3__SIZE 0x0000000au
#define CYREG_SAR_RANGE_THRES 0x403a0018u
#define CYFLD_SAR_RANGE_LOW__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_LOW__SIZE 0x00000010u
#define CYFLD_SAR_RANGE_HIGH__OFFSET 0x00000010u
#define CYFLD_SAR_RANGE_HIGH__SIZE 0x00000010u
#define CYREG_SAR_RANGE_COND 0x403a001cu
#define CYFLD_SAR_RANGE_COND__OFFSET 0x0000001eu
#define CYFLD_SAR_RANGE_COND__SIZE 0x00000002u
#define CYVAL_SAR_RANGE_COND_BELOW 0x00000000u
#define CYVAL_SAR_RANGE_COND_INSIDE 0x00000001u
#define CYVAL_SAR_RANGE_COND_ABOVE 0x00000002u
#define CYVAL_SAR_RANGE_COND_OUTSIDE 0x00000003u
#define CYREG_SAR_CHAN_EN 0x403a0020u
#define CYFLD_SAR_CHAN_EN__OFFSET 0x00000000u
#define CYFLD_SAR_CHAN_EN__SIZE 0x00000010u
#define CYREG_SAR_START_CTRL 0x403a0024u
#define CYFLD_SAR_FW_TRIGGER__OFFSET 0x00000000u
#define CYFLD_SAR_FW_TRIGGER__SIZE 0x00000001u
#define CYREG_SAR_DFT_CTRL 0x403a0030u
#define CYFLD_SAR_DLY_INC__OFFSET 0x00000000u
#define CYFLD_SAR_DLY_INC__SIZE 0x00000001u
#define CYFLD_SAR_HIZ__OFFSET 0x00000001u
#define CYFLD_SAR_HIZ__SIZE 0x00000001u
#define CYFLD_SAR_DFT_INC__OFFSET 0x00000010u
#define CYFLD_SAR_DFT_INC__SIZE 0x00000004u
#define CYFLD_SAR_DFT_OUTC__OFFSET 0x00000014u
#define CYFLD_SAR_DFT_OUTC__SIZE 0x00000003u
#define CYFLD_SAR_SEL_CSEL_DFT__OFFSET 0x00000018u
#define CYFLD_SAR_SEL_CSEL_DFT__SIZE 0x00000004u
#define CYFLD_SAR_EN_CSEL_DFT__OFFSET 0x0000001cu
#define CYFLD_SAR_EN_CSEL_DFT__SIZE 0x00000001u
#define CYFLD_SAR_DCEN__OFFSET 0x0000001du
#define CYFLD_SAR_DCEN__SIZE 0x00000001u
#define CYFLD_SAR_ADFT_OVERRIDE__OFFSET 0x0000001fu
#define CYFLD_SAR_ADFT_OVERRIDE__SIZE 0x00000001u
#define CYREG_SAR_CHAN_CONFIG0 0x403a0080u
#define CYFLD_SAR_PIN_ADDR__OFFSET 0x00000000u
#define CYFLD_SAR_PIN_ADDR__SIZE 0x00000003u
#define CYFLD_SAR_PORT_ADDR__OFFSET 0x00000004u
#define CYFLD_SAR_PORT_ADDR__SIZE 0x00000003u
#define CYVAL_SAR_PORT_ADDR_SARMUX 0x00000000u
#define CYVAL_SAR_PORT_ADDR_CTB0 0x00000001u
#define CYVAL_SAR_PORT_ADDR_CTB1 0x00000002u
#define CYVAL_SAR_PORT_ADDR_CTB2 0x00000003u
#define CYVAL_SAR_PORT_ADDR_CTB3 0x00000004u
#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT2 0x00000005u
#define CYVAL_SAR_PORT_ADDR_AROUTE_VIRT1 0x00000006u
#define CYVAL_SAR_PORT_ADDR_SARMUX_VIRT 0x00000007u
#define CYFLD_SAR_DIFFERENTIAL_EN__OFFSET 0x00000008u
#define CYFLD_SAR_DIFFERENTIAL_EN__SIZE 0x00000001u
#define CYFLD_SAR_RESOLUTION__OFFSET 0x00000009u
#define CYFLD_SAR_RESOLUTION__SIZE 0x00000001u
#define CYVAL_SAR_RESOLUTION_MAXRES 0x00000000u
#define CYVAL_SAR_RESOLUTION_SUBRES 0x00000001u
#define CYFLD_SAR_AVG_EN__OFFSET 0x0000000au
#define CYFLD_SAR_AVG_EN__SIZE 0x00000001u
#define CYFLD_SAR_SAMPLE_TIME_SEL__OFFSET 0x0000000cu
#define CYFLD_SAR_SAMPLE_TIME_SEL__SIZE 0x00000002u
#define CYFLD_SAR_DSI_OUT_EN__OFFSET 0x0000001fu
#define CYFLD_SAR_DSI_OUT_EN__SIZE 0x00000001u
#define CYREG_SAR_CHAN_CONFIG1 0x403a0084u
#define CYREG_SAR_CHAN_CONFIG2 0x403a0088u
#define CYREG_SAR_CHAN_CONFIG3 0x403a008cu
#define CYREG_SAR_CHAN_CONFIG4 0x403a0090u
#define CYREG_SAR_CHAN_CONFIG5 0x403a0094u
#define CYREG_SAR_CHAN_CONFIG6 0x403a0098u
#define CYREG_SAR_CHAN_CONFIG7 0x403a009cu
#define CYREG_SAR_CHAN_CONFIG8 0x403a00a0u
#define CYREG_SAR_CHAN_CONFIG9 0x403a00a4u
#define CYREG_SAR_CHAN_CONFIG10 0x403a00a8u
#define CYREG_SAR_CHAN_CONFIG11 0x403a00acu
#define CYREG_SAR_CHAN_CONFIG12 0x403a00b0u
#define CYREG_SAR_CHAN_CONFIG13 0x403a00b4u
#define CYREG_SAR_CHAN_CONFIG14 0x403a00b8u
#define CYREG_SAR_CHAN_CONFIG15 0x403a00bcu
#define CYREG_SAR_CHAN_WORK0 0x403a0100u
#define CYFLD_SAR_WORK__OFFSET 0x00000000u
#define CYFLD_SAR_WORK__SIZE 0x00000010u
#define CYFLD_SAR_CHAN_WORK_VALID_MIR__OFFSET 0x0000001fu
#define CYFLD_SAR_CHAN_WORK_VALID_MIR__SIZE 0x00000001u
#define CYREG_SAR_CHAN_WORK1 0x403a0104u
#define CYREG_SAR_CHAN_WORK2 0x403a0108u
#define CYREG_SAR_CHAN_WORK3 0x403a010cu
#define CYREG_SAR_CHAN_WORK4 0x403a0110u
#define CYREG_SAR_CHAN_WORK5 0x403a0114u
#define CYREG_SAR_CHAN_WORK6 0x403a0118u
#define CYREG_SAR_CHAN_WORK7 0x403a011cu
#define CYREG_SAR_CHAN_WORK8 0x403a0120u
#define CYREG_SAR_CHAN_WORK9 0x403a0124u
#define CYREG_SAR_CHAN_WORK10 0x403a0128u
#define CYREG_SAR_CHAN_WORK11 0x403a012cu
#define CYREG_SAR_CHAN_WORK12 0x403a0130u
#define CYREG_SAR_CHAN_WORK13 0x403a0134u
#define CYREG_SAR_CHAN_WORK14 0x403a0138u
#define CYREG_SAR_CHAN_WORK15 0x403a013cu
#define CYREG_SAR_CHAN_RESULT0 0x403a0180u
#define CYFLD_SAR_RESULT__OFFSET 0x00000000u
#define CYFLD_SAR_RESULT__SIZE 0x00000010u
#define CYFLD_SAR_SATURATE_INTR_MIR__OFFSET 0x0000001du
#define CYFLD_SAR_SATURATE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_RANGE_INTR_MIR__OFFSET 0x0000001eu
#define CYFLD_SAR_RANGE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__OFFSET 0x0000001fu
#define CYFLD_SAR_CHAN_RESULT_VALID_MIR__SIZE 0x00000001u
#define CYREG_SAR_CHAN_RESULT1 0x403a0184u
#define CYREG_SAR_CHAN_RESULT2 0x403a0188u
#define CYREG_SAR_CHAN_RESULT3 0x403a018cu
#define CYREG_SAR_CHAN_RESULT4 0x403a0190u
#define CYREG_SAR_CHAN_RESULT5 0x403a0194u
#define CYREG_SAR_CHAN_RESULT6 0x403a0198u
#define CYREG_SAR_CHAN_RESULT7 0x403a019cu
#define CYREG_SAR_CHAN_RESULT8 0x403a01a0u
#define CYREG_SAR_CHAN_RESULT9 0x403a01a4u
#define CYREG_SAR_CHAN_RESULT10 0x403a01a8u
#define CYREG_SAR_CHAN_RESULT11 0x403a01acu
#define CYREG_SAR_CHAN_RESULT12 0x403a01b0u
#define CYREG_SAR_CHAN_RESULT13 0x403a01b4u
#define CYREG_SAR_CHAN_RESULT14 0x403a01b8u
#define CYREG_SAR_CHAN_RESULT15 0x403a01bcu
#define CYREG_SAR_CHAN_WORK_VALID 0x403a0200u
#define CYFLD_SAR_CHAN_WORK_VALID__OFFSET 0x00000000u
#define CYFLD_SAR_CHAN_WORK_VALID__SIZE 0x00000010u
#define CYREG_SAR_CHAN_RESULT_VALID 0x403a0204u
#define CYFLD_SAR_CHAN_RESULT_VALID__OFFSET 0x00000000u
#define CYFLD_SAR_CHAN_RESULT_VALID__SIZE 0x00000010u
#define CYREG_SAR_STATUS 0x403a0208u
#define CYFLD_SAR_CUR_CHAN__OFFSET 0x00000000u
#define CYFLD_SAR_CUR_CHAN__SIZE 0x00000005u
#define CYFLD_SAR_SW_VREF_NEG__OFFSET 0x0000001eu
#define CYFLD_SAR_SW_VREF_NEG__SIZE 0x00000001u
#define CYFLD_SAR_BUSY__OFFSET 0x0000001fu
#define CYFLD_SAR_BUSY__SIZE 0x00000001u
#define CYREG_SAR_AVG_STAT 0x403a020cu
#define CYFLD_SAR_CUR_AVG_ACCU__OFFSET 0x00000000u
#define CYFLD_SAR_CUR_AVG_ACCU__SIZE 0x00000014u
#define CYFLD_SAR_CUR_AVG_CNT__OFFSET 0x00000018u
#define CYFLD_SAR_CUR_AVG_CNT__SIZE 0x00000008u
#define CYREG_SAR_INTR 0x403a0210u
#define CYFLD_SAR_EOS_INTR__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_INTR__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_INTR__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_INTR__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_INTR__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_INTR__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_INTR__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_INTR__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_INTR__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_INTR__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_INTR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_INTR__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_INTR__SIZE 0x00000001u
#define CYREG_SAR_INTR_SET 0x403a0214u
#define CYFLD_SAR_EOS_SET__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_SET__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_SET__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_SET__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_SET__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_SET__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_SET__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_SET__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_SET__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_SET__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_SET__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_SET__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_SET__SIZE 0x00000001u
#define CYREG_SAR_INTR_MASK 0x403a0218u
#define CYFLD_SAR_EOS_MASK__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_MASK__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASK__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASK__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_MASK__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_MASK__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_MASK__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_MASK__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_MASK__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_MASK__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_MASK__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_MASK__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_MASK__SIZE 0x00000001u
#define CYREG_SAR_INTR_MASKED 0x403a021cu
#define CYFLD_SAR_EOS_MASKED__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_MASKED__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_MASKED__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_MASKED__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_MASKED__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_MASKED__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_MASKED__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_MASKED__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_MASKED__SIZE 0x00000001u
#define CYREG_SAR_SATURATE_INTR 0x403a0220u
#define CYFLD_SAR_SATURATE_INTR__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_INTR__SIZE 0x00000010u
#define CYREG_SAR_SATURATE_INTR_SET 0x403a0224u
#define CYFLD_SAR_SATURATE_SET__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_SET__SIZE 0x00000010u
#define CYREG_SAR_SATURATE_INTR_MASK 0x403a0228u
#define CYFLD_SAR_SATURATE_MASK__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_MASK__SIZE 0x00000010u
#define CYREG_SAR_SATURATE_INTR_MASKED 0x403a022cu
#define CYFLD_SAR_SATURATE_MASKED__OFFSET 0x00000000u
#define CYFLD_SAR_SATURATE_MASKED__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR 0x403a0230u
#define CYFLD_SAR_RANGE_INTR__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_INTR__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR_SET 0x403a0234u
#define CYFLD_SAR_RANGE_SET__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_SET__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR_MASK 0x403a0238u
#define CYFLD_SAR_RANGE_MASK__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_MASK__SIZE 0x00000010u
#define CYREG_SAR_RANGE_INTR_MASKED 0x403a023cu
#define CYFLD_SAR_RANGE_MASKED__OFFSET 0x00000000u
#define CYFLD_SAR_RANGE_MASKED__SIZE 0x00000010u
#define CYREG_SAR_INTR_CAUSE 0x403a0240u
#define CYFLD_SAR_EOS_MASKED_MIR__OFFSET 0x00000000u
#define CYFLD_SAR_EOS_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED_MIR__OFFSET 0x00000001u
#define CYFLD_SAR_OVERFLOW_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__OFFSET 0x00000002u
#define CYFLD_SAR_FW_COLLISION_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__OFFSET 0x00000003u
#define CYFLD_SAR_DSI_COLLISION_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_MASKED_MIR__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_EOC_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__OFFSET 0x00000005u
#define CYFLD_SAR_INJ_SATURATE_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__OFFSET 0x00000006u
#define CYFLD_SAR_INJ_RANGE_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__OFFSET 0x00000007u
#define CYFLD_SAR_INJ_COLLISION_MASKED_MIR__SIZE 0x00000001u
#define CYFLD_SAR_SATURATE_MASKED_RED__OFFSET 0x0000001eu
#define CYFLD_SAR_SATURATE_MASKED_RED__SIZE 0x00000001u
#define CYFLD_SAR_RANGE_MASKED_RED__OFFSET 0x0000001fu
#define CYFLD_SAR_RANGE_MASKED_RED__SIZE 0x00000001u
#define CYREG_SAR_INJ_CHAN_CONFIG 0x403a0280u
#define CYFLD_SAR_INJ_PIN_ADDR__OFFSET 0x00000000u
#define CYFLD_SAR_INJ_PIN_ADDR__SIZE 0x00000003u
#define CYFLD_SAR_INJ_PORT_ADDR__OFFSET 0x00000004u
#define CYFLD_SAR_INJ_PORT_ADDR__SIZE 0x00000003u
#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX 0x00000000u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB0 0x00000001u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB1 0x00000002u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB2 0x00000003u
#define CYVAL_SAR_INJ_PORT_ADDR_CTB3 0x00000004u
#define CYVAL_SAR_INJ_PORT_ADDR_AROUTE_VIRT 0x00000006u
#define CYVAL_SAR_INJ_PORT_ADDR_SARMUX_VIRT 0x00000007u
#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__OFFSET 0x00000008u
#define CYFLD_SAR_INJ_DIFFERENTIAL_EN__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RESOLUTION__OFFSET 0x00000009u
#define CYFLD_SAR_INJ_RESOLUTION__SIZE 0x00000001u
#define CYVAL_SAR_INJ_RESOLUTION_12B 0x00000000u
#define CYVAL_SAR_INJ_RESOLUTION_SUBRES 0x00000001u
#define CYFLD_SAR_INJ_AVG_EN__OFFSET 0x0000000au
#define CYFLD_SAR_INJ_AVG_EN__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__OFFSET 0x0000000cu
#define CYFLD_SAR_INJ_SAMPLE_TIME_SEL__SIZE 0x00000002u
#define CYFLD_SAR_INJ_TAILGATING__OFFSET 0x0000001eu
#define CYFLD_SAR_INJ_TAILGATING__SIZE 0x00000001u
#define CYFLD_SAR_INJ_START_EN__OFFSET 0x0000001fu
#define CYFLD_SAR_INJ_START_EN__SIZE 0x00000001u
#define CYREG_SAR_INJ_RESULT 0x403a0290u
#define CYFLD_SAR_INJ_RESULT__OFFSET 0x00000000u
#define CYFLD_SAR_INJ_RESULT__SIZE 0x00000010u
#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__OFFSET 0x0000001cu
#define CYFLD_SAR_INJ_COLLISION_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__OFFSET 0x0000001du
#define CYFLD_SAR_INJ_SATURATE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_RANGE_INTR_MIR__OFFSET 0x0000001eu
#define CYFLD_SAR_INJ_RANGE_INTR_MIR__SIZE 0x00000001u
#define CYFLD_SAR_INJ_EOC_INTR_MIR__OFFSET 0x0000001fu
#define CYFLD_SAR_INJ_EOC_INTR_MIR__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH0 0x403a0300u
#define CYFLD_SAR_MUX_FW_P0_VPLUS__OFFSET 0x00000000u
#define CYFLD_SAR_MUX_FW_P0_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P1_VPLUS__OFFSET 0x00000001u
#define CYFLD_SAR_MUX_FW_P1_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P2_VPLUS__OFFSET 0x00000002u
#define CYFLD_SAR_MUX_FW_P2_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P3_VPLUS__OFFSET 0x00000003u
#define CYFLD_SAR_MUX_FW_P3_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P4_VPLUS__OFFSET 0x00000004u
#define CYFLD_SAR_MUX_FW_P4_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_VPLUS__OFFSET 0x00000005u
#define CYFLD_SAR_MUX_FW_P5_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P6_VPLUS__OFFSET 0x00000006u
#define CYFLD_SAR_MUX_FW_P6_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P7_VPLUS__OFFSET 0x00000007u
#define CYFLD_SAR_MUX_FW_P7_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P0_VMINUS__OFFSET 0x00000008u
#define CYFLD_SAR_MUX_FW_P0_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P1_VMINUS__OFFSET 0x00000009u
#define CYFLD_SAR_MUX_FW_P1_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P2_VMINUS__OFFSET 0x0000000au
#define CYFLD_SAR_MUX_FW_P2_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P3_VMINUS__OFFSET 0x0000000bu
#define CYFLD_SAR_MUX_FW_P3_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P4_VMINUS__OFFSET 0x0000000cu
#define CYFLD_SAR_MUX_FW_P4_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_VMINUS__OFFSET 0x0000000du
#define CYFLD_SAR_MUX_FW_P5_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P6_VMINUS__OFFSET 0x0000000eu
#define CYFLD_SAR_MUX_FW_P6_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P7_VMINUS__OFFSET 0x0000000fu
#define CYFLD_SAR_MUX_FW_P7_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__OFFSET 0x00000010u
#define CYFLD_SAR_MUX_FW_VSSA_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__OFFSET 0x00000011u
#define CYFLD_SAR_MUX_FW_TEMP_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__OFFSET 0x00000012u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__OFFSET 0x00000013u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__OFFSET 0x00000014u
#define CYFLD_SAR_MUX_FW_AMUXBUSA_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__OFFSET 0x00000015u
#define CYFLD_SAR_MUX_FW_AMUXBUSB_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__OFFSET 0x00000016u
#define CYFLD_SAR_MUX_FW_SARBUS0_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__OFFSET 0x00000017u
#define CYFLD_SAR_MUX_FW_SARBUS1_VPLUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__OFFSET 0x00000018u
#define CYFLD_SAR_MUX_FW_SARBUS0_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__OFFSET 0x00000019u
#define CYFLD_SAR_MUX_FW_SARBUS1_VMINUS__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P4_COREIO0__OFFSET 0x0000001au
#define CYFLD_SAR_MUX_FW_P4_COREIO0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_COREIO1__OFFSET 0x0000001bu
#define CYFLD_SAR_MUX_FW_P5_COREIO1__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P6_COREIO2__OFFSET 0x0000001cu
#define CYFLD_SAR_MUX_FW_P6_COREIO2__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P7_COREIO3__OFFSET 0x0000001du
#define CYFLD_SAR_MUX_FW_P7_COREIO3__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH_CLEAR0 0x403a0304u
#define CYREG_SAR_MUX_SWITCH1 0x403a0308u
#define CYFLD_SAR_MUX_FW_P4_DFT_INP__OFFSET 0x00000000u
#define CYFLD_SAR_MUX_FW_P4_DFT_INP__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_DFT_INM__OFFSET 0x00000001u
#define CYFLD_SAR_MUX_FW_P5_DFT_INM__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__OFFSET 0x00000002u
#define CYFLD_SAR_MUX_FW_ADFT0_SARBUS0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__OFFSET 0x00000003u
#define CYFLD_SAR_MUX_FW_ADFT1_SARBUS1__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH_CLEAR1 0x403a030cu
#define CYREG_SAR_MUX_SWITCH_HW_CTRL 0x403a0340u
#define CYFLD_SAR_MUX_HW_CTRL_P0__OFFSET 0x00000000u
#define CYFLD_SAR_MUX_HW_CTRL_P0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P1__OFFSET 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P1__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P2__OFFSET 0x00000002u
#define CYFLD_SAR_MUX_HW_CTRL_P2__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P3__OFFSET 0x00000003u
#define CYFLD_SAR_MUX_HW_CTRL_P3__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P4__OFFSET 0x00000004u
#define CYFLD_SAR_MUX_HW_CTRL_P4__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P5__OFFSET 0x00000005u
#define CYFLD_SAR_MUX_HW_CTRL_P5__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P6__OFFSET 0x00000006u
#define CYFLD_SAR_MUX_HW_CTRL_P6__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_P7__OFFSET 0x00000007u
#define CYFLD_SAR_MUX_HW_CTRL_P7__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_VSSA__OFFSET 0x00000010u
#define CYFLD_SAR_MUX_HW_CTRL_VSSA__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_TEMP__OFFSET 0x00000011u
#define CYFLD_SAR_MUX_HW_CTRL_TEMP__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__OFFSET 0x00000012u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSA__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__OFFSET 0x00000013u
#define CYFLD_SAR_MUX_HW_CTRL_AMUXBUSB__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__OFFSET 0x00000016u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS0__SIZE 0x00000001u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__OFFSET 0x00000017u
#define CYFLD_SAR_MUX_HW_CTRL_SARBUS1__SIZE 0x00000001u
#define CYREG_SAR_MUX_SWITCH_STATUS 0x403a0348u
#define CYREG_SAR_PUMP_CTRL 0x403a0380u
#define CYFLD_SAR_CLOCK_SEL__OFFSET 0x00000000u
#define CYFLD_SAR_CLOCK_SEL__SIZE 0x00000001u
#define CYREG_SAR_ANA_TRIM 0x403a0f00u
#define CYFLD_SAR_CAP_TRIM__OFFSET 0x00000000u
#define CYFLD_SAR_CAP_TRIM__SIZE 0x00000003u
#define CYFLD_SAR_TRIMUNIT__OFFSET 0x00000003u
#define CYFLD_SAR_TRIMUNIT__SIZE 0x00000001u
#define CYREG_SAR_WOUNDING 0x403a0f04u
#define CYFLD_SAR_WOUND_RESOLUTION__OFFSET 0x00000000u
#define CYFLD_SAR_WOUND_RESOLUTION__SIZE 0x00000002u
#define CYVAL_SAR_WOUND_RESOLUTION_12BIT 0x00000000u
#define CYVAL_SAR_WOUND_RESOLUTION_10BIT 0x00000001u
#define CYVAL_SAR_WOUND_RESOLUTION_8BIT 0x00000002u
#define CYVAL_SAR_WOUND_RESOLUTION_8BIT_TOO 0x00000003u
#define CYDEV_PASS_BASE 0x403f0000u
#define CYDEV_PASS_SIZE 0x00010000u
#define CYREG_PASS_INTR_CAUSE 0x403f0000u
#define CYFLD_PASS_CTB0_INT__OFFSET 0x00000000u
#define CYFLD_PASS_CTB0_INT__SIZE 0x00000001u
#define CYREG_PASS_DFT_CTRL 0x403f0030u
#define CYFLD_PASS_DSAB_ADFT_RES_EN__OFFSET 0x00000000u
#define CYFLD_PASS_DSAB_ADFT_RES_EN__SIZE 0x00000001u
#define CYREG_PASS_PASS_CTRL 0x403f0108u
#define CYFLD_PASS_PMPCLK_BYP__OFFSET 0x00000000u
#define CYFLD_PASS_PMPCLK_BYP__SIZE 0x00000001u
#define CYFLD_PASS_PMPCLK_SRC__OFFSET 0x00000001u
#define CYFLD_PASS_PMPCLK_SRC__SIZE 0x00000001u
#define CYFLD_PASS_RMB_BITS__OFFSET 0x00000008u
#define CYFLD_PASS_RMB_BITS__SIZE 0x00000008u
#define CYDEV_PASS_DSAB_BASE 0x403f0e00u
#define CYDEV_PASS_DSAB_SIZE 0x00000100u
#define CYREG_PASS_DSAB_DSAB_CTRL 0x403f0e00u
#define CYFLD_PASS_DSAB_CURRENT_SEL__OFFSET 0x00000000u
#define CYFLD_PASS_DSAB_CURRENT_SEL__SIZE 0x00000006u
#define CYFLD_PASS_DSAB_SEL_OUT__OFFSET 0x00000008u
#define CYFLD_PASS_DSAB_SEL_OUT__SIZE 0x00000004u
#define CYFLD_PASS_DSAB_REF_SWAP_EN__OFFSET 0x00000010u
#define CYFLD_PASS_DSAB_REF_SWAP_EN__SIZE 0x00000004u
#define CYFLD_PASS_DSAB_BYPASS_MODE_EN__OFFSET 0x00000018u
#define CYFLD_PASS_DSAB_BYPASS_MODE_EN__SIZE 0x00000001u
#define CYFLD_PASS_DSAB_STARTUP_RM__OFFSET 0x0000001cu
#define CYFLD_PASS_DSAB_STARTUP_RM__SIZE 0x00000001u
#define CYFLD_PASS_DSAB_ENABLED__OFFSET 0x0000001fu
#define CYFLD_PASS_DSAB_ENABLED__SIZE 0x00000001u
#define CYREG_PASS_DSAB_DSAB_DFT 0x403f0e04u
#define CYFLD_PASS_DSAB_EN_DFT__OFFSET 0x00000000u
#define CYFLD_PASS_DSAB_EN_DFT__SIZE 0x00000004u
#define CYREG_PASS_DSAB_TRIM 0x403f0f00u
#define CYFLD_PASS_IBIAS_TRIM__OFFSET 0x00000000u
#define CYFLD_PASS_IBIAS_TRIM__SIZE 0x00000004u
#define CYFLD_PASS_DSAB_RMB_BITS__OFFSET 0x00000004u
#define CYFLD_PASS_DSAB_RMB_BITS__SIZE 0x00000002u
#define CYDEV_CM0P_BASE 0xe0000000u
#define CYDEV_CM0P_SIZE 0x00100000u
#define CYREG_CM0P_DWT_PID4 0xe0001fd0u
#define CYFLD_CM0P_VALUE__OFFSET 0x00000000u
#define CYFLD_CM0P_VALUE__SIZE 0x00000020u
#define CYREG_CM0P_DWT_PID0 0xe0001fe0u
#define CYREG_CM0P_DWT_PID1 0xe0001fe4u
#define CYREG_CM0P_DWT_PID2 0xe0001fe8u
#define CYREG_CM0P_DWT_PID3 0xe0001fecu
#define CYREG_CM0P_DWT_CID0 0xe0001ff0u
#define CYREG_CM0P_DWT_CID1 0xe0001ff4u
#define CYREG_CM0P_DWT_CID2 0xe0001ff8u
#define CYREG_CM0P_DWT_CID3 0xe0001ffcu
#define CYREG_CM0P_BP_PID4 0xe0002fd0u
#define CYREG_CM0P_BP_PID0 0xe0002fe0u
#define CYREG_CM0P_BP_PID1 0xe0002fe4u
#define CYREG_CM0P_BP_PID2 0xe0002fe8u
#define CYREG_CM0P_BP_PID3 0xe0002fecu
#define CYREG_CM0P_BP_CID0 0xe0002ff0u
#define CYREG_CM0P_BP_CID1 0xe0002ff4u
#define CYREG_CM0P_BP_CID2 0xe0002ff8u
#define CYREG_CM0P_BP_CID3 0xe0002ffcu
#define CYREG_CM0P_SYST_CSR 0xe000e010u
#define CYFLD_CM0P_ENABLE__OFFSET 0x00000000u
#define CYFLD_CM0P_ENABLE__SIZE 0x00000001u
#define CYFLD_CM0P_TICKINT__OFFSET 0x00000001u
#define CYFLD_CM0P_TICKINT__SIZE 0x00000001u
#define CYFLD_CM0P_CLKSOURCE__OFFSET 0x00000002u
#define CYFLD_CM0P_CLKSOURCE__SIZE 0x00000001u
#define CYFLD_CM0P_COUNTFLAG__OFFSET 0x00000010u
#define CYFLD_CM0P_COUNTFLAG__SIZE 0x00000001u
#define CYREG_CM0P_SYST_RVR 0xe000e014u
#define CYFLD_CM0P_RELOAD__OFFSET 0x00000000u
#define CYFLD_CM0P_RELOAD__SIZE 0x00000018u
#define CYREG_CM0P_SYST_CVR 0xe000e018u
#define CYFLD_CM0P_CURRENT__OFFSET 0x00000000u
#define CYFLD_CM0P_CURRENT__SIZE 0x00000018u
#define CYREG_CM0P_SYST_CALIB 0xe000e01cu
#define CYFLD_CM0P_TENMS__OFFSET 0x00000000u
#define CYFLD_CM0P_TENMS__SIZE 0x00000018u
#define CYFLD_CM0P_SKEW__OFFSET 0x0000001eu
#define CYFLD_CM0P_SKEW__SIZE 0x00000001u
#define CYFLD_CM0P_NOREF__OFFSET 0x0000001fu
#define CYFLD_CM0P_NOREF__SIZE 0x00000001u
#define CYREG_CM0P_ISER 0xe000e100u
#define CYFLD_CM0P_SETENA__OFFSET 0x00000000u
#define CYFLD_CM0P_SETENA__SIZE 0x00000020u
#define CYREG_CM0P_ICER 0xe000e180u
#define CYFLD_CM0P_CLRENA__OFFSET 0x00000000u
#define CYFLD_CM0P_CLRENA__SIZE 0x00000020u
#define CYREG_CM0P_ISPR 0xe000e200u
#define CYFLD_CM0P_SETPEND__OFFSET 0x00000000u
#define CYFLD_CM0P_SETPEND__SIZE 0x00000020u
#define CYREG_CM0P_ICPR 0xe000e280u
#define CYFLD_CM0P_CLRPEND__OFFSET 0x00000000u
#define CYFLD_CM0P_CLRPEND__SIZE 0x00000020u
#define CYREG_CM0P_IPR0 0xe000e400u
#define CYFLD_CM0P_PRI_N0__OFFSET 0x00000006u
#define CYFLD_CM0P_PRI_N0__SIZE 0x00000002u
#define CYFLD_CM0P_PRI_N1__OFFSET 0x0000000eu
#define CYFLD_CM0P_PRI_N1__SIZE 0x00000002u
#define CYFLD_CM0P_PRI_N2__OFFSET 0x00000016u
#define CYFLD_CM0P_PRI_N2__SIZE 0x00000002u
#define CYFLD_CM0P_PRI_N3__OFFSET 0x0000001eu
#define CYFLD_CM0P_PRI_N3__SIZE 0x00000002u
#define CYREG_CM0P_IPR1 0xe000e404u
#define CYREG_CM0P_IPR2 0xe000e408u
#define CYREG_CM0P_IPR3 0xe000e40cu
#define CYREG_CM0P_IPR4 0xe000e410u
#define CYREG_CM0P_IPR5 0xe000e414u
#define CYREG_CM0P_IPR6 0xe000e418u
#define CYREG_CM0P_IPR7 0xe000e41cu
#define CYREG_CM0P_CPUID 0xe000ed00u
#define CYFLD_CM0P_REVISION__OFFSET 0x00000000u
#define CYFLD_CM0P_REVISION__SIZE 0x00000004u
#define CYFLD_CM0P_PARTNO__OFFSET 0x00000004u
#define CYFLD_CM0P_PARTNO__SIZE 0x0000000cu
#define CYFLD_CM0P_CONSTANT__OFFSET 0x00000010u
#define CYFLD_CM0P_CONSTANT__SIZE 0x00000004u
#define CYFLD_CM0P_VARIANT__OFFSET 0x00000014u
#define CYFLD_CM0P_VARIANT__SIZE 0x00000004u
#define CYFLD_CM0P_IMPLEMENTER__OFFSET 0x00000018u
#define CYFLD_CM0P_IMPLEMENTER__SIZE 0x00000008u
#define CYREG_CM0P_ICSR 0xe000ed04u
#define CYFLD_CM0P_VECTACTIVE__OFFSET 0x00000000u
#define CYFLD_CM0P_VECTACTIVE__SIZE 0x00000009u
#define CYFLD_CM0P_VECTPENDING__OFFSET 0x0000000cu
#define CYFLD_CM0P_VECTPENDING__SIZE 0x00000009u
#define CYFLD_CM0P_ISRPENDING__OFFSET 0x00000016u
#define CYFLD_CM0P_ISRPENDING__SIZE 0x00000001u
#define CYFLD_CM0P_ISRPREEMPT__OFFSET 0x00000017u
#define CYFLD_CM0P_ISRPREEMPT__SIZE 0x00000001u
#define CYFLD_CM0P_PENDSTCLR__OFFSET 0x00000019u
#define CYFLD_CM0P_PENDSTCLR__SIZE 0x00000001u
#define CYFLD_CM0P_PENDSTSETb__OFFSET 0x0000001au
#define CYFLD_CM0P_PENDSTSETb__SIZE 0x00000001u
#define CYFLD_CM0P_PENDSVCLR__OFFSET 0x0000001bu
#define CYFLD_CM0P_PENDSVCLR__SIZE 0x00000001u
#define CYFLD_CM0P_PENDSVSET__OFFSET 0x0000001cu
#define CYFLD_CM0P_PENDSVSET__SIZE 0x00000001u
#define CYFLD_CM0P_NMIPENDSET__OFFSET 0x0000001fu
#define CYFLD_CM0P_NMIPENDSET__SIZE 0x00000001u
#define CYREG_CM0P_VTOR 0xe000ed08u
#define CYFLD_CM0P_TBLOFF__OFFSET 0x00000008u
#define CYFLD_CM0P_TBLOFF__SIZE 0x00000018u
#define CYREG_CM0P_AIRCR 0xe000ed0cu
#define CYFLD_CM0P_VECTCLRACTIVE__OFFSET 0x00000001u
#define CYFLD_CM0P_VECTCLRACTIVE__SIZE 0x00000001u
#define CYFLD_CM0P_SYSRESETREQ__OFFSET 0x00000002u
#define CYFLD_CM0P_SYSRESETREQ__SIZE 0x00000001u
#define CYFLD_CM0P_ENDIANNESS__OFFSET 0x0000000fu
#define CYFLD_CM0P_ENDIANNESS__SIZE 0x00000001u
#define CYFLD_CM0P_VECTKEY__OFFSET 0x00000010u
#define CYFLD_CM0P_VECTKEY__SIZE 0x00000010u
#define CYREG_CM0P_SCR 0xe000ed10u
#define CYFLD_CM0P_SLEEPONEXIT__OFFSET 0x00000001u
#define CYFLD_CM0P_SLEEPONEXIT__SIZE 0x00000001u
#define CYFLD_CM0P_SLEEPDEEP__OFFSET 0x00000002u
#define CYFLD_CM0P_SLEEPDEEP__SIZE 0x00000001u
#define CYFLD_CM0P_SEVONPEND__OFFSET 0x00000004u
#define CYFLD_CM0P_SEVONPEND__SIZE 0x00000001u
#define CYREG_CM0P_CCR 0xe000ed14u
#define CYFLD_CM0P_UNALIGN_TRP__OFFSET 0x00000003u
#define CYFLD_CM0P_UNALIGN_TRP__SIZE 0x00000001u
#define CYFLD_CM0P_STKALIGN__OFFSET 0x00000009u
#define CYFLD_CM0P_STKALIGN__SIZE 0x00000001u
#define CYREG_CM0P_SHPR2 0xe000ed1cu
#define CYFLD_CM0P_PRI_11__OFFSET 0x0000001eu
#define CYFLD_CM0P_PRI_11__SIZE 0x00000002u
#define CYREG_CM0P_SHPR3 0xe000ed20u
#define CYFLD_CM0P_PRI_14__OFFSET 0x00000016u
#define CYFLD_CM0P_PRI_14__SIZE 0x00000002u
#define CYFLD_CM0P_PRI_15__OFFSET 0x0000001eu
#define CYFLD_CM0P_PRI_15__SIZE 0x00000002u
#define CYREG_CM0P_SHCSR 0xe000ed24u
#define CYFLD_CM0P_SVCALLPENDED__OFFSET 0x0000000fu
#define CYFLD_CM0P_SVCALLPENDED__SIZE 0x00000001u
#define CYREG_CM0P_SCS_PID4 0xe000efd0u
#define CYREG_CM0P_SCS_PID0 0xe000efe0u
#define CYREG_CM0P_SCS_PID1 0xe000efe4u
#define CYREG_CM0P_SCS_PID2 0xe000efe8u
#define CYREG_CM0P_SCS_PID3 0xe000efecu
#define CYREG_CM0P_SCS_CID0 0xe000eff0u
#define CYREG_CM0P_SCS_CID1 0xe000eff4u
#define CYREG_CM0P_SCS_CID2 0xe000eff8u
#define CYREG_CM0P_SCS_CID3 0xe000effcu
#define CYREG_CM0P_ROM_SCS 0xe00ff000u
#define CYREG_CM0P_ROM_DWT 0xe00ff004u
#define CYREG_CM0P_ROM_BPU 0xe00ff008u
#define CYREG_CM0P_ROM_END 0xe00ff00cu
#define CYREG_CM0P_ROM_CSMT 0xe00fffccu
#define CYREG_CM0P_ROM_PID4 0xe00fffd0u
#define CYREG_CM0P_ROM_PID0 0xe00fffe0u
#define CYREG_CM0P_ROM_PID1 0xe00fffe4u
#define CYREG_CM0P_ROM_PID2 0xe00fffe8u
#define CYREG_CM0P_ROM_PID3 0xe00fffecu
#define CYREG_CM0P_ROM_CID0 0xe00ffff0u
#define CYREG_CM0P_ROM_CID1 0xe00ffff4u
#define CYREG_CM0P_ROM_CID2 0xe00ffff8u
#define CYREG_CM0P_ROM_CID3 0xe00ffffcu
#define CYDEV_ROMTABLE_BASE 0xf0000000u
#define CYDEV_ROMTABLE_SIZE 0x00001000u
#define CYREG_ROMTABLE_ADDR 0xf0000000u
#define CYFLD_ROMTABLE_PRESENT__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_PRESENT__SIZE 0x00000001u
#define CYFLD_ROMTABLE_FORMAT_32BIT__OFFSET 0x00000001u
#define CYFLD_ROMTABLE_FORMAT_32BIT__SIZE 0x00000001u
#define CYFLD_ROMTABLE_ADDR_OFFSET__OFFSET 0x0000000cu
#define CYFLD_ROMTABLE_ADDR_OFFSET__SIZE 0x00000014u
#define CYREG_ROMTABLE_DID 0xf0000fccu
#define CYFLD_ROMTABLE_VALUE__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_VALUE__SIZE 0x00000020u
#define CYREG_ROMTABLE_PID4 0xf0000fd0u
#define CYFLD_ROMTABLE_JEP_CONTINUATION__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_JEP_CONTINUATION__SIZE 0x00000004u
#define CYFLD_ROMTABLE_COUNT__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_COUNT__SIZE 0x00000004u
#define CYREG_ROMTABLE_PID5 0xf0000fd4u
#define CYREG_ROMTABLE_PID6 0xf0000fd8u
#define CYREG_ROMTABLE_PID7 0xf0000fdcu
#define CYREG_ROMTABLE_PID0 0xf0000fe0u
#define CYFLD_ROMTABLE_PN_MIN__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_PN_MIN__SIZE 0x00000008u
#define CYREG_ROMTABLE_PID1 0xf0000fe4u
#define CYFLD_ROMTABLE_PN_MAJ__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_PN_MAJ__SIZE 0x00000004u
#define CYFLD_ROMTABLE_JEPID_MIN__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_JEPID_MIN__SIZE 0x00000004u
#define CYREG_ROMTABLE_PID2 0xf0000fe8u
#define CYFLD_ROMTABLE_JEPID_MAJ__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_JEPID_MAJ__SIZE 0x00000003u
#define CYFLD_ROMTABLE_REV__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_REV__SIZE 0x00000004u
#define CYREG_ROMTABLE_PID3 0xf0000fecu
#define CYFLD_ROMTABLE_CM__OFFSET 0x00000000u
#define CYFLD_ROMTABLE_CM__SIZE 0x00000004u
#define CYFLD_ROMTABLE_REV_AND__OFFSET 0x00000004u
#define CYFLD_ROMTABLE_REV_AND__SIZE 0x00000004u
#define CYREG_ROMTABLE_CID0 0xf0000ff0u
#define CYREG_ROMTABLE_CID1 0xf0000ff4u
#define CYREG_ROMTABLE_CID2 0xf0000ff8u
#define CYREG_ROMTABLE_CID3 0xf0000ffcu
#define CYDEV_FLS_SECTOR_SIZE 0x00020000u
#define CYDEV_FLS_ROW_SIZE 0x00000100u
#endif /* CYDEVICE_TRM_H */
